diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..5d116e6 --- /dev/null +++ b/.gitignore @@ -0,0 +1,24 @@ +*.o +*.a +.depend + +System.map +board/scb9520/config.tmp +include/asm +include/asm-arm/arch +include/asm-arm/proc +include/bmp_logo.h +include/config.h +include/config.mk +include/version_autogenerated.h +tools/bmp_logo +tools/crc32.c +tools/envcrc +tools/environment.c +tools/gen_eth_addr +tools/img2srec +tools/mkimage +u-boot +u-boot.bin +u-boot.map +u-boot.srec diff --git a/Makefile b/Makefile index a973dff..532a8b6 100644 --- a/Makefile +++ b/Makefile @@ -122,7 +122,7 @@ ifeq ($(HOSTARCH),ppc) CROSS_COMPILE = else ifeq ($(ARCH),ppc) -CROSS_COMPILE = powerpc-linux- +CROSS_COMPILE = powerpc-unknown-linux-gnu- endif ifeq ($(ARCH),arm) CROSS_COMPILE = arm-linux- @@ -220,7 +220,6 @@ PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) - # The "tools" are needed early, so put this first # Don't include stuff already done in $(LIBS) SUBDIRS = tools \ - examples \ post \ post/cpu .PHONY : $(SUBDIRS) @@ -1913,8 +1912,32 @@ omap730p2_cs3boot_config : unconfig sbc2410x_config: unconfig @$(MKCONFIG) $(@:_config=) arm arm920t sbc2410x NULL s3c24x0 -scb9328_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm920t scb9328 NULL imx +scb9328_config scb9324_config : unconfig + @mkdir -p $(obj)include + @ >$(obj)include/config.h + @if [ "$(findstring 9328, $@)" ] ; then \ + echo "#define BOARD_SCB9328 " >> $(obj)include/config.h ; \ + else \ + echo "#define BOARD_SCB9324 " >> $(obj)include/config.h ; \ + fi; + @$(MKCONFIG) -a scb9328 arm arm920t scb9328 NULL imx + +scb9520_config \ +scb9520_64MB_config \ +scb9520_128MB_config : unconfig + @mkdir -p $(obj)include + @mkdir -p $(obj)board/scb9520 + @ >$(obj)include/config.h + @if [ "$(findstring _64MB_, $@)" ] ; then \ + echo "#define CONFIG_64MB " >> $(obj)include/config.h ; \ + echo "TEXT_BASE = 0xa7fd0000" >$(obj)board/scb9520/config.tmp ; \ + echo "... configured for 64MB"; \ + else \ + echo "#define CONFIG_128MB " >> $(obj)include/config.h ; \ + echo "TEXT_BASE = 0xa1fd0000" >$(obj)board/scb9520/config.tmp ; \ + echo "... configured for 128MB"; \ + fi; + @$(MKCONFIG) -a $(call xtract_scb9520,$@) arm pxa scb9520 smdk2400_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm920t smdk2400 NULL s3c24x0 @@ -2074,6 +2097,8 @@ xsengine_config : unconfig zylonite_config : @$(MKCONFIG) $(@:_config=) arm pxa zylonite +xtract_scb9520 = $(subst _64MB,,$(subst _128MB,,$(subst _config,,$1))) + ######################################################################### ## ARM1136 Systems ######################################################################### diff --git a/board/scb9328/Makefile b/board/scb9328/Makefile index 85b6b04..4add2fc 100644 --- a/board/scb9328/Makefile +++ b/board/scb9328/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := scb9328.o flash.o +COBJS := scb9328.o SOBJS := lowlevel_init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/scb9328/config.mk b/board/scb9328/config.mk index 8d1d79a..0e0b089 100644 --- a/board/scb9328/config.mk +++ b/board/scb9328/config.mk @@ -8,3 +8,4 @@ # TEXT_BASE = 0x08f00000 +PLATFORM_CPPFLAGS += -mno-thumb-interwork diff --git a/board/scb9328/lowlevel_init.S b/board/scb9328/lowlevel_init.S index ba3b6d2..826c993 100644 --- a/board/scb9328/lowlevel_init.S +++ b/board/scb9328/lowlevel_init.S @@ -22,12 +22,56 @@ #include #include +.macro ledon + ldr r0, =0x0021C120 + ldr r1, =0x00B00000 + str r1, [r0] + + ldr r0, =0x0021C108 + ldr r1, =0x0000FC00 + str r1, [r0] + + ldr r0, =0x0021C11C + ldr r1, =0xFF7FFFFF + str r1, [r0] + + ldr r0, =0x0021C100 + ldr r1, =0x00B00000 + str r1, [r0] +.endm + .globl lowlevel_init lowlevel_init: mov r10, lr -/* Change PERCLK1DIV to 14 ie 14+1 */ +/* change General EIM config Register to set driving strength */ + ldr r0, =GPCR + ldr r1, =CFG_GPCR_VAL + str r1, [r0] + +#ifdef CONFIG_SCB9328_LEDON + ledon +#endif + +/* crystal coming up time workaround */ + ldr r0, = 0x00223010 + ldr r1, = 0x08000000 + str r1, [r0] + + ldr r0, = 0x00202008 + ldr r1, = 0x00000800 + str r1, [r0] + + ldr r0, = 0x00202000 + ldr r1, = 0x0000001f + str r1, [r0] + + ldr r0, = 0x0021B000 + ldr r1, = 0x2b000800 + str r1, [r0] + +/* Change PERCLK divider */ ldr r0, =PCDR ldr r1, =CFG_PCDR_VAL str r1, [r0] @@ -80,35 +124,20 @@ lowlevel_init: ldr r1, =CFG_CSCR_VAL str r1, [r0] -/* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon - *this..... +/* * - * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15 + * from a Cold-Boot the ARM920T enters "FastBus" mode CP15 * register 1, this stops it using the output of the PLL and thus runs at the * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never * use the value set in the CM_OSC registers...regardless of what you set it - * too! Thus, although i thought i was running at 140MHz, i'm actually running - * at 40!.. - - * Slapping this into my bootloader does the trick... - - * MRC p15,0,r0,c1,c0,0 ; read core configuration register - * ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode - * MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration - * register + * too! + * ORR r0,r0,#0xC0000000 async mode + * ORR r0,r0,#0x40000000 sync mode */ MRC p15,0,r0,c1,c0,0 ORR r0,r0,#0xC0000000 MCR p15,0,r0,c1,c0,0 - ldr r0, =GPR(0) - ldr r1, =CFG_GPR_A_VAL - str r1, [r0] - - ldr r0, =GIUS(0) - ldr r1, =CFG_GIUS_A_VAL - str r1, [r0] - /* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */ ldr r0, =FMCR @@ -119,9 +148,11 @@ lowlevel_init: ldr r1, =CFG_CS0U_VAL str r1, [r0] +/* we get this from EIM_BOOT_SETTINGS ldr r0, =CS0L ldr r1, =CFG_CS0L_VAL str r1, [r0] +*/ ldr r0, =CS1U ldr r1, =CFG_CS1U_VAL @@ -147,6 +178,7 @@ lowlevel_init: ldr r1, =CFG_CS3L_VAL str r1, [r0] +#ifdef CONFIG_DRIVER_NAND ldr r0, =CS4U ldr r1, =CFG_CS4U_VAL str r1, [r0] @@ -154,6 +186,17 @@ lowlevel_init: ldr r0, =CS4L ldr r1, =CFG_CS4L_VAL str r1, [r0] +#endif + +#ifdef CONFIG_DRIVER_DM9000 +/* CS5 is PA23 on powerup */ + ldr r0, =GPR(0) + ldr r1, =CFG_GPR_A_VAL + str r1, [r0] + + ldr r0, =GIUS(0) + ldr r1, =CFG_GIUS_A_VAL + str r1, [r0] ldr r0, =CS5U ldr r1, =CFG_CS5U_VAL @@ -162,11 +205,12 @@ lowlevel_init: ldr r0, =CS5L ldr r1, =CFG_CS5L_VAL str r1, [r0] +#endif /* SDRAM Setup */ ldr r0, =SDCTL0 - ldr r1, =PRECHARGE_CMD + ldr r1, =(SDCTL0_VAL | SMODE_PRECHARGE) str r1, [r0] ldr r0, =0x08200000 @@ -174,7 +218,7 @@ lowlevel_init: str r1, [r0] ldr r0, =SDCTL0 - ldr r1, =AUTOREFRESH_CMD + ldr r1, =(SDCTL0_VAL | SMODE_AUTOREFRESH) str r1, [r0] ldr r0, =0x08000000 @@ -189,15 +233,37 @@ lowlevel_init: str r1, [r0] ldr r0, =SDCTL0 - ldr r1, =0xb10a8300 + ldr r1, =(SDCTL0_VAL | SMODE_MODEREG) str r1, [r0] - ldr r0, =0x08223000 /* CAS Latency 2 */ - ldr r1, =0x0 /* Issue Mode Register Command, Burst Length = 8 */ + ldr r0, =SEND_MREG_CMD + ldr r1, =0x0 /* Issue Mode Register Command */ str r1, [r0] ldr r0, =SDCTL0 - ldr r1, =0x810a8200 /* Set to Normal Mode CAS 2 */ + ldr r1, =(SDCTL0_VAL | SMODE_NORMAL) /* Set Normal Mode */ str r1, [r0] +#ifdef CONFIG_SCB9328_TOGGLELED + mov r6,#0x5 +3: + ldr r8, =0x14000000 + ldr r9, =0x00000000 + str r9, [r8] + mov r7,#0x300000 +2: + subs r7,r7,#1 + bne 2b + + ldr r8, =0x14000000 + ldr r9, =0x55000000 + str r9, [r8] + mov r7,#0x300000 +1: + subs r7,r7,#1 + bne 1b + subs r6,r6,#1 + bne 3b +#endif + mov pc,r10 diff --git a/board/scb9328/scb9328.c b/board/scb9328/scb9328.c index 3f6831b..ad0d9e9 100644 --- a/board/scb9328/scb9328.c +++ b/board/scb9328/scb9328.c @@ -19,6 +19,7 @@ */ #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -32,6 +33,7 @@ int board_init (void) { gd->bd->bi_arch_number = MACH_TYPE_SCB9328; gd->bd->bi_boot_params = 0x08000100; + silent_boot(); return 0; } @@ -57,16 +59,136 @@ int dram_init (void) return 0; } -/** - * show_boot_progress: - indicate state of the boot process - * - * @param status: Status number - see README for details. - * - * The CSB226 does only have 3 LEDs, so we switch them on at the most - * important states (1, 5, 15). - */ +int silent_boot (void) +{ + DECLARE_GLOBAL_DATA_PTR; + int serial; + + imx_gpio_mode( GPIO_PORTA | GPIO_IN | GPIO_PUEN | 15 ); + /* get level of pin50 DIL64 SDA aka GPIO A 15 */ + serial = __REG(0x21c024); + if ( serial & 0x00008000 ) { + } else { + gd->flags |= GD_FLG_SILENT; + } + return 0; +} + +int misc_init_r (void) +{ + +#ifdef CONFIG_IMX_DBG + setenv("verify", "y"); +#else + setenv("verify", "n"); +// burst_on(); +#endif + + uchar *str, *s; + int status, button; + + s = getenv ("button"); + button = (s && (*s == 'n')) ? 0 : 1; + + if (button == 1) { + + /* get level of VM pin DIL64 pin 49 aka GPIO B 25) */ + imx_gpio_mode( GPIO_PORTB | GPIO_IN | GPIO_PUEN | 25 ); + + status = __REG(0x21c124); +#ifdef CONFIG_IMX_DBG + printf("SSR_B (requesting status): 0x%08lx\n", status); +#endif + if ( status & 0x02000000 ) { +#ifdef CONFIG_IMX_DBG + printf("using bootcmd (sw-update button not pressed)\n"); +#endif + str = "bootm 0x10040000"; + } else { + printf("stopping autoboot (sw-update button pressed)\n"); + str = getenv("bootcmd_stop"); + } + + setenv("bootcmd",str); + + }else{ +#ifdef CONFIG_IMX_DBG + printf("to enable button request set button to y(es)\n"); + setenv("bootcmd", "bootm 0x10040000"); +#endif + } + pme_on(); + return (0); +} + +int raise(void) +{ + return 0; +} + +#ifdef CONFIG_DRIVER_NAND +extern void imx_gpio_mode(int gpio_mode); +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_IMX_DBG + +#ifdef CONFIG_DRIVER_NAND + u8 nandstatus; + u8 makercode; + u8 devicecode; + u8 data3; + u8 data4; + u8 data5; + + imx_gpio_mode (22 | GPIO_PF | GPIO_PORTA); + imx_gpio_mode (17 | GPIO_OUT | GPIO_GPIO | GPIO_PORTB); + imx_gpio_mode (18 | GPIO_OUT | GPIO_GPIO | GPIO_PORTB); + + DR(1) &= ~(1<<17); + DR(1) &= ~(1<<18); + + DR(1) |= (1<<17); *(volatile u8 *)(CONFIG_NAND_BASE) = 0xff; DR(1) &= ~(1<<17); + DR(1) |= (1<<17); *(volatile u8 *)(CONFIG_NAND_BASE + (1 << 20)) = 0xff; DR(1) &= ~(1<<17); + DR(1) |= (1<<17); *(volatile u8 *)(CONFIG_NAND_BASE) = 0x70; DR(1) &= ~(1<<17); + nandstatus = *(volatile u8 *)(CONFIG_NAND_BASE); + DR(1) |= (1<<17); *(volatile u8 *)(CONFIG_NAND_BASE) = 0x90; DR(1) &= ~(1<<17); + DR(1) |= (1<<18); *(volatile u8 *)(CONFIG_NAND_BASE) = 0x00; DR(1) &= ~(1<<18); + makercode = *(volatile u8 *)(CONFIG_NAND_BASE); + devicecode = *(volatile u8 *)(CONFIG_NAND_BASE); + data3 = *(volatile u8 *)(CONFIG_NAND_BASE); + data4 = *(volatile u8 *)(CONFIG_NAND_BASE); + data5 = *(volatile u8 *)(CONFIG_NAND_BASE); + + printf("NAND Flash status: 0x%02x\n", nandstatus & 0xff); + printf("NAND Flash makercode: 0x%02x\n", makercode & 0xff); + printf("NAND Flash devicecode: 0x%02x\n", devicecode & 0xff); + printf("NAND Flash data3: 0x%02x\n", data3 & 0xff); + printf("NAND Flash data4: 0x%02x\n", data4 & 0xff); + printf("NAND Flash data5: 0x%02x\n", data5 & 0xff); +#endif /* CONFIG_DRIVER_NAND */ + + printf("system PLL: %9u\n", get_systemPLLCLK()); + printf("mcu freq: %9u\n", get_FCLK()); + printf("bclk: %9u\n", get_BCLK()); + printf("perclk1: %9u\n", get_PERCLK1()); + printf("perclk2: %9u\n", get_PERCLK2()); + printf("perclk3: %9u\n", get_PERCLK3()); + printf("TCTL1: 0x%08x\n", TCTL1); + printf("TPRER1: 0x%08x\n", TPRER1); + printf("CSCR: 0x%08x\n", CSCR); + printf("PCDR: 0x%08x\n", PCDR); + printf("SPCTL0: 0x%08x\n", SPCTL0); + printf("MPCTL0: 0x%08x\n", MPCTL0); +#endif /* defined (CONFIG_IMX_DBG) */ + + return 0; +} void show_boot_progress (int status) { + printf("bootprogress status: %i\n", status); + return; } diff --git a/board/scb9520/Makefile b/board/scb9520/Makefile new file mode 100644 index 0000000..1de61e9 --- /dev/null +++ b/board/scb9520/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/scb9520/config.mk b/board/scb9520/config.mk new file mode 100644 index 0000000..c6f6898 --- /dev/null +++ b/board/scb9520/config.mk @@ -0,0 +1,2 @@ +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp +PLATFORM_CPPFLAGS += -mno-thumb-interwork diff --git a/board/scb9520/intel.h b/board/scb9520/intel.h new file mode 100644 index 0000000..77498b6 --- /dev/null +++ b/board/scb9520/intel.h @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2002 ETC s.r.o. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the ETC s.r.o. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Written by Marcel Telka , 2002. + * + * Documentation: + * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A, + * 28F320J3A (x8/x16)", April 2002, Order Number: 290667-011 + * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18, + * 28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005 + * + * This file is taken from OpenWinCE project hosted by SourceForge.net + * + */ + +#ifndef FLASH_INTEL_H +#define FLASH_INTEL_H + +#include + +/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */ + +#define CFI_INTEL_CMD_READ_ARRAY 0xFF /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_READ_IDENTIFIER 0x90 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_READ_QUERY 0x98 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_READ_STATUS_REGISTER 0x70 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_CLEAR_STATUS_REGISTER 0x50 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_PROGRAM1 0x40 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_PROGRAM2 0x10 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_WRITE_TO_BUFFER 0xE8 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_CONFIRM 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_BLOCK_ERASE 0x20 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_SUSPEND 0xB0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_RESUME 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_LOCK_SETUP 0x60 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_LOCK_BLOCK 0x01 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_UNLOCK_BLOCK 0xD0 /* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_LOCK_DOWN_BLOCK 0x2F /* 28FxxxK3, 28FxxxK18 */ + +/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */ + +#define CFI_INTEL_SR_READY 1 << 7 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_ERASE_SUSPEND 1 << 6 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_ERASE_ERROR 1 << 5 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_PROGRAM_ERROR 1 << 4 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_VPEN_ERROR 1 << 3 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_PROGRAM_SUSPEND 1 << 2 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_BLOCK_LOCKED 1 << 1 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_BEFP 1 << 0 /* 28FxxxK3, 28FxxxK18 */ + +/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */ + +#define CFI_CHIP_INTEL_28F320J3A 0x0016 +#define CFI_CHIPN_INTEL_28F320J3A "28F320J3A" +#define CFI_CHIP_INTEL_28F640J3A 0x0017 +#define CFI_CHIPN_INTEL_28F640J3A "28F640J3A" +#define CFI_CHIP_INTEL_28F128J3A 0x0018 +#define CFI_CHIPN_INTEL_28F128J3A "28F128J3A" + +/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */ + +#define CFI_CHIP_INTEL_28F640K3 0x8801 +#define CFI_CHIPN_INTEL_28F640K3 "28F640K3" +#define CFI_CHIP_INTEL_28F128K3 0x8802 +#define CFI_CHIPN_INTEL_28F128K3 "28F128K3" +#define CFI_CHIP_INTEL_28F256K3 0x8803 +#define CFI_CHIPN_INTEL_28F256K3 "28F256K3" +#define CFI_CHIP_INTEL_28F640K18 0x8805 +#define CFI_CHIPN_INTEL_28F640K18 "28F640K18" +#define CFI_CHIP_INTEL_28F128K18 0x8806 +#define CFI_CHIPN_INTEL_28F128K18 "28F128K18" +#define CFI_CHIP_INTEL_28F256K18 0x8807 +#define CFI_CHIPN_INTEL_28F256K18 "28F256K18" + +#endif /* FLASH_INTEL_H */ diff --git a/board/scb9520/lowlevel_init.S b/board/scb9520/lowlevel_init.S new file mode 100644 index 0000000..736cad4 --- /dev/null +++ b/board/scb9520/lowlevel_init.S @@ -0,0 +1,523 @@ +/* + * This was originally from the Lubbock u-boot port. + * + * Most of this taken from Redboot hal_platform_setup.h with cleanup + * + * NOTE: I haven't clean this up considerably, just enough to get it + * running. See hal_platform_setup.h for the source. See + * board/cradle/lowlevel_init.S for another PXA250 setup that is + * much cleaner. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* wait for coprocessor write complete */ + .macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 + .endm + + +/* + * Memory setup + */ + +.globl lowlevel_init +lowlevel_init: + + /* Set up GPIO pins first ----------------------------------------- */ + + ldr r0, =GPSR0 + ldr r1, =CFG_GPSR0_VAL + str r1, [r0] + + ldr r0, =GPSR1 + ldr r1, =CFG_GPSR1_VAL + str r1, [r0] + + ldr r0, =GPSR2 + ldr r1, =CFG_GPSR2_VAL + str r1, [r0] + + ldr r0, =GPSR3 + ldr r1, =CFG_GPSR3_VAL + str r1, [r0] + + ldr r0, =GPCR0 + ldr r1, =CFG_GPCR0_VAL + str r1, [r0] + + ldr r0, =GPCR1 + ldr r1, =CFG_GPCR1_VAL + str r1, [r0] + + ldr r0, =GPCR2 + ldr r1, =CFG_GPCR2_VAL + str r1, [r0] + + ldr r0, =GPCR3 + ldr r1, =CFG_GPCR3_VAL + str r1, [r0] + + ldr r0, =GPDR0 + ldr r1, =CFG_GPDR0_VAL + str r1, [r0] + + ldr r0, =GPDR1 + ldr r1, =CFG_GPDR1_VAL + str r1, [r0] + + ldr r0, =GPDR2 + ldr r1, =CFG_GPDR2_VAL + str r1, [r0] + + ldr r0, =GPDR3 + ldr r1, =CFG_GPDR3_VAL + str r1, [r0] + + ldr r0, =GAFR0_L + ldr r1, =CFG_GAFR0_L_VAL + str r1, [r0] + + ldr r0, =GAFR0_U + ldr r1, =CFG_GAFR0_U_VAL + str r1, [r0] + + ldr r0, =GAFR1_L + ldr r1, =CFG_GAFR1_L_VAL + str r1, [r0] + + ldr r0, =GAFR1_U + ldr r1, =CFG_GAFR1_U_VAL + str r1, [r0] + + ldr r0, =GAFR2_L + ldr r1, =CFG_GAFR2_L_VAL + str r1, [r0] + + ldr r0, =GAFR2_U + ldr r1, =CFG_GAFR2_U_VAL + str r1, [r0] + + ldr r0, =GAFR3_L + ldr r1, =CFG_GAFR3_L_VAL + str r1, [r0] + + ldr r0, =GAFR3_U + ldr r1, =CFG_GAFR3_U_VAL + str r1, [r0] + + ldr r0, =PSSR /* enable GPIO pins */ + ldr r1, =CFG_PSSR_VAL + str r1, [r0] + + /* ---------------------------------------------------------------- */ + /* Enable memory interface */ + /* */ + /* The sequence below is based on the recommended init steps */ + /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ + /* Chapter 10. */ + /* ---------------------------------------------------------------- */ + + /* ---------------------------------------------------------------- */ + /* Step 1: Wait for at least 200 microsedonds to allow internal */ + /* clocks to settle. Only necessary after hard reset... */ + /* FIXME: can be optimized later */ + /* ---------------------------------------------------------------- */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + +mem_init: + + ldr r1, =MEMC_BASE /* get memory controller base addr. */ + + /* Set driving strength of all pins */ + + ldr r2, =CFG_BSCNTR_VAL + str r2, [r1, #BSCNTR0_OFFSET] + str r2, [r1, #BSCNTR1_OFFSET] + str r2, [r1, #BSCNTR2_OFFSET] + str r2, [r1, #BSCNTR3_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2a: Initialize Asynchronous static memory controller */ + /* ---------------------------------------------------------------- */ + + /* MSC registers: timing, bus width, mem type */ + + /* MSC0: nCS(0,1) */ + ldr r2, =CFG_MSC0_VAL + str r2, [r1, #MSC0_OFFSET] + ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ + /* that data latches */ + /* MSC1: nCS(2,3) */ + ldr r2, =CFG_MSC1_VAL + str r2, [r1, #MSC1_OFFSET] + ldr r2, [r1, #MSC1_OFFSET] + + /* MSC2: nCS(4,5) */ + ldr r2, =CFG_MSC2_VAL + str r2, [r1, #MSC2_OFFSET] + ldr r2, [r1, #MSC2_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2b: Initialize Card Interface */ + /* ---------------------------------------------------------------- */ + + /* MECR: Memory Expansion Card Register */ + ldr r2, =CFG_MECR_VAL + str r2, [r1, #MECR_OFFSET] + ldr r2, [r1, #MECR_OFFSET] + + /* MCMEM0: Card Interface slot 0 timing */ + ldr r2, =CFG_MCMEM0_VAL + str r2, [r1, #MCMEM0_OFFSET] + ldr r2, [r1, #MCMEM0_OFFSET] + + /* MCMEM1: Card Interface slot 1 timing */ + ldr r2, =CFG_MCMEM1_VAL + str r2, [r1, #MCMEM1_OFFSET] + ldr r2, [r1, #MCMEM1_OFFSET] + + /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ + ldr r2, =CFG_MCATT0_VAL + str r2, [r1, #MCATT0_OFFSET] + ldr r2, [r1, #MCATT0_OFFSET] + + /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ + ldr r2, =CFG_MCATT1_VAL + str r2, [r1, #MCATT1_OFFSET] + ldr r2, [r1, #MCATT1_OFFSET] + + /* MCIO0: Card Interface I/O Space Timing, slot 0 */ + ldr r2, =CFG_MCIO0_VAL + str r2, [r1, #MCIO0_OFFSET] + ldr r2, [r1, #MCIO0_OFFSET] + + /* MCIO1: Card Interface I/O Space Timing, slot 1 */ + ldr r2, =CFG_MCIO1_VAL + str r2, [r1, #MCIO1_OFFSET] + ldr r2, [r1, #MCIO1_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2c: Write FLYCNFG FIXME: what's that??? */ + /* ---------------------------------------------------------------- */ + ldr r2, =CFG_FLYCNFG_VAL + str r2, [r1, #FLYCNFG_OFFSET] + str r2, [r1, #FLYCNFG_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ + /* ---------------------------------------------------------------- */ + + /* Before accessing MDREFR we need a valid DRI field, so we set */ + /* this to power on defaults + DRI field. */ + + ldr r4, [r1, #MDREFR_OFFSET] + ldr r2, =0xFFF + bic r4, r4, r2 + + ldr r3, =CFG_MDREFR_VAL + and r3, r3, r2 + + orr r4, r4, r3 + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + + orr r4, r4, #MDREFR_K0RUN + orr r4, r4, #MDREFR_K0DB4 + orr r4, r4, #MDREFR_K0FREE + orr r4, r4, #MDREFR_K2FREE + orr r4, r4, #MDREFR_K0DB2 + orr r4, r4, #MDREFR_K1DB2 + bic r4, r4, #MDREFR_K1FREE + + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + + + /* ---------------------------------------------------------------- */ + /* Step 4: Initialize SDRAM */ + /* ---------------------------------------------------------------- */ + + bic r4, r4, #(MDREFR_K1FREE | MDREFR_K0FREE) + + orr r4, r4, #MDREFR_K1RUN + orr r4, r4, #MDREFR_K2FREE + bic r4, r4, #MDREFR_K2DB2 + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + bic r4, r4, #MDREFR_SLFRSH + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + orr r4, r4, #MDREFR_E1PIN + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + nop + nop + + /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ + /* configure but not enable each SDRAM partition pair. */ + + ldr r4, =CFG_MDCNFG_VAL + bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) + bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3) + + ldr r4, =CFG_MDCNFG_VAL + + str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ + ldr r4, [r1, #MDCNFG_OFFSET] + + /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ + /* 100..200 µsec. */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + + + /* Step 4f: Trigger a number (usually 8) refresh cycles by */ + /* attempting non-burst read or write accesses to disabled */ + /* SDRAM, as commonly specified in the power up sequence */ + /* documented in SDRAM data sheets. The address(es) used */ + /* for this purpose must not be cacheable. */ + + ldr r3, =CFG_SDRAM_1 + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] +#ifndef CONFIG_64MB + ldr r3, =CFG_SDRAM_2 + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] +#endif + + /* Step 4g: Write MDCNFG with enable bits asserted */ + /* (MDCNFG:DEx set to 1). */ + + ldr r3, [r1, #MDCNFG_OFFSET] + mov r4, r3 + orr r3, r3, #MDCNFG_DE0 + str r3, [r1, #MDCNFG_OFFSET] + mov r0, r3 + + /* Step 4h: Write MDMRS. */ + + ldr r2, =CFG_MDMRS_VAL + str r2, [r1, #MDMRS_OFFSET] + + /* enable APD */ + ldr r3, [r1, #MDREFR_OFFSET] + orr r3, r3, #MDREFR_APD + str r3, [r1, #MDREFR_OFFSET] + + /* We are finished with Intel's memory controller initialisation */ + +wakeup: + /* Are we waking from sleep? */ + ldr r0, =RCSR + ldr r1, [r0] + and r1, r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR) + str r1, [r0] + teq r1, #RCSR_SMR + + bne initirqs + + ldr r0, =PSSR + mov r1, #PSSR_PH + str r1, [r0] + + /* if so, resume at PSPR */ + ldr r0, =PSPR + ldr r1, [r0] + mov pc, r1 + + /* ---------------------------------------------------------------- */ + /* Disable (mask) all interrupts at interrupt controller */ + /* ---------------------------------------------------------------- */ + +initirqs: + + mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ + ldr r2, =ICLR + str r1, [r2] + + ldr r2, =ICMR /* mask all interrupts at the controller */ + str r1, [r2] + + /* ---------------------------------------------------------------- */ + /* Clock initialisation */ + /* ---------------------------------------------------------------- */ + +initclks: + + /* Disable the peripheral clocks, and set the core clock frequency */ + + /* Turn Off on-chip peripheral clocks (except for memory) */ + /* for re-configuration. */ + ldr r1, =CKEN + ldr r2, =CFG_CKEN + str r2, [r1] + + /* ... and write the core clock config register */ + ldr r2, =CFG_CCCR + ldr r1, =CCCR + str r2, [r1] + + /* Turn on turbo mode */ + mrc p14, 0, r2, c6, c0, 0 + orr r2, r2, #0xB /* Turbo, Fast-Bus, Freq change**/ + mcr p14, 0, r2, c6, c0, 0 + + /* Re-write MDREFR */ + ldr r1, =MEMC_BASE + ldr r2, [r1, #MDREFR_OFFSET] + str r2, [r1, #MDREFR_OFFSET] +#ifdef RTC + /* enable the 32Khz oscillator for RTC and PowerManager */ + ldr r1, =OSCC + mov r2, #OSCC_OON + str r2, [r1] +#else +#error "RTC not defined" +#endif + + /* Interrupt init: Mask all interrupts */ + ldr r0, =ICMR /* enable no sources */ + mov r1, #0 + str r1, [r0] + /* FIXME */ + +#ifdef NODEBUG + /*Disable software and data breakpoints */ + mov r0,#0 + mcr p15,0,r0,c14,c8,0 /* ibcr0 */ + mcr p15,0,r0,c14,c9,0 /* ibcr1 */ + mcr p15,0,r0,c14,c4,0 /* dbcon */ + + /*Enable all debug functionality */ + mov r0,#0x80000000 + mcr p14,0,r0,c10,c0,0 /* dcsr */ +#endif + +initializei2c: + + ldr r2, =CKEN + ldr r3, [r2] + orr r3, r3, #CKEN15_PWRI2C + str r3, [r2] + + ldr r2, =PCFR + ldr r3, [r2] + orr r3, r3, #PCFR_PI2C_EN + str r3, [r2] + + /* delay for about 250msec + */ + ldr r3, =OSCR + mov r2, #0 + str r2, [r3] + ldr r1, =0xC0000 +1: + ldr r2, [r3] + cmp r1, r2 + bgt 1b + ldr r0, =PWRICR + ldr r1, [r0] + bic r1, r1, #(ICR_MA | ICR_START | ICR_STOP) + str r1, [r0] + + orr r1, r1, #ICR_UR + str r1, [r0] + + ldr r2, =PWRISR + ldr r3, =0x7ff + str r3, [r2] + + bic r1, r1, #ICR_UR + str r1, [r0] + + mov r1, #(ICR_GCD | ICR_SCLE) + str r1, [r0] + + orr r1, r1, #ICR_IUE + str r1, [r0] + + orr r1, r1, #ICR_FM + str r1, [r0] + + /* delay for about 1msec + */ + ldr r3, =OSCR + mov r2, #0 + str r2, [r3] + ldr r1, =0xC00 + +1: + ldr r2, [r3] + cmp r1, r2 + bgt 1b + mov pc, lr + + + /* ---------------------------------------------------------------- */ + /* End lowlevel_init */ + /* ---------------------------------------------------------------- */ + +endlowlevel_init: +#if 0 + ldr r0,=GPDR2 + ldr r1,=CFG_GPDR2_VAL + and r1,r1,#0xFBFFFFFF /* switch off LED0 (GPIO 90) */ + str r1,[r0] +#endif + mov pc, lr diff --git a/board/scb9520/scb9520.c b/board/scb9520/scb9520.c new file mode 100644 index 0000000..f6432f6 --- /dev/null +++ b/board/scb9520/scb9520.c @@ -0,0 +1,189 @@ +/* + * Copyright (C) 2003 ETC s.r.o. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Written by Peter Figuli , 2003. + * + */ + +#include +#include +#include "scb9520.h" + +int board_init( void ){ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_arch_number = MACH_TYPE_SCB9520; +#ifdef CONFIG_128MB + gd->bd->bi_boot_params = 0xa0000100; +#else + gd->bd->bi_boot_params = 0xa4000100; +#endif + gd->bd->bi_baudrate = CONFIG_BAUDRATE; + silent_boot(); +#if (SCB9520_USE_IDE==1) + /* IDE Drive */ + /* Enable IDE Latches */ + __SCB9520_IDE_PLD_REG(SCB9520_IDE_PLD_PHYS + SCB9520_IDE_PLD_REG3) = + SCB9520_IDE_IDEOE + SCB9520_IDE_IDEON + SCB9520_IDE_IDEIN; + + /* Enable Power */ + __SCB9520_IDE_PLD_REG(SCB9520_IDE_PLD_PHYS + SCB9520_IDE_PLD_REG4) = + SCB9520_IDE_PWRENA; + + /* Some harddisks need some time for it's initialization. + * Therefore the next delay of 5s. */ +#endif + +#if (SCB9520_USE_LCD==1) + /* LCD Display */ + /* Enable LCD and Power */ + __SCB9520_CTRL_REG(SCB9520_CTRL_PHYS + SCB9520_CTRL_REG3) = + SCB9520_CTRL_LCDPWR + SCB9520_CTRL_LCDON; +#endif + return 0; +} + +/** + * i2c_init_board - reset i2c bus. When the board is powercycled during a + * bus transfer it might hang; for details see doc/I2C_Edge_Conditions. + * The Phytec board has GPIO117 connected to SCLK which can be toggled + * until all chips think that their current cycles are finished. + */ +int i2c_init_board(void) +{ + int i, icr; + + set_GPIO_mode(GPIO117_SCL); + set_GPIO_mode(GPIO118_SDA); + + /* disable I2C controller first, otherwhise it thinks we want to */ + /* talk to the slave port... */ + icr = ICR; + ICR &= ~(ICR_SCLE | ICR_IUE); + + /* set gpio pin low _before_ we change direction to output */ + GPCR(117) = GPIO_bit(117); + + /* now toggle between output=low and high-impedance */ + for (i = 0; i < 20; i++) { + GPDR(117) |= GPIO_bit(117); /* output */ + udelay(10); + GPDR(117) &= ~GPIO_bit(117); /* input */ + udelay(10); + } + + ICR = icr; +} + +int silent_boot (void) +{ + DECLARE_GLOBAL_DATA_PTR; + int serial; + + serial = *(volatile ushort *)(PXA_CS4_PHYS + 0x2); + /* get level of MA0 and read from CPLD */ + if ( serial & 0x00000080 ) { + } else { + gd->flags |= GD_FLG_SILENT; + } + return 0; +} + +int misc_init_r(void) +{ + ushort nand_status, makercode, devicecode, dontcare, status2; + printf("resetting NAND Flash\n"); + +/* +1. CLE=0, ALE=0, CEx = 1 +2. CLE=1, ALE=0, CEx = 1 +3. Reset Kommando schreiben (0xFF) +4. CLE=0, ALE=0, CEx = 0 +5. dasselbe für das 2. Chip-Select Signal + +i.e. + +mw.w 10000002 0x59 (p33_NAND_CE1 -> active, CLE = '1') +mw.w 10000000 0xFF (command RESET) +mw.w 10000002 0x01 (p33_NAND_CE1 -> active, CLE = '0') + +mw.w 10000002 0x0A (p33_NAND_CE2 -> active, CLE = '1') +mw.w 10000000 0xFF (command RESET) +mw.w 10000002 0x02 (p33_NAND_CE2 -> active, CLE = '0') + +mw.w 10000002 0x00 +*/ + *(volatile ushort *)(PXA_CS4_PHYS + 2) = 0x59; + *(volatile ushort *)(PXA_CS4_PHYS + 0) = 0xff; + *(volatile ushort *)(PXA_CS4_PHYS + 2) = 0x01; + *(volatile ushort *)(PXA_CS4_PHYS + 2) = 0x0a; + *(volatile ushort *)(PXA_CS4_PHYS + 0) = 0xff; + *(volatile ushort *)(PXA_CS4_PHYS + 2) = 0x01; + *(volatile ushort *)(PXA_CS4_PHYS + 2) = 0x00; + +/* now read the status register */ + *(volatile ushort *)(PXA_CS4_PHYS + 2) = 0x59; + *(volatile ushort *)(PXA_CS4_PHYS + 0) = 0x70; + *(volatile ushort *)(PXA_CS4_PHYS + 2) = 0x01; + nand_status = *(volatile ushort *)(PXA_CS4_PHYS + 0x00000000); + printf("read status %x\n", nand_status); + +/* now read the makercode and deviceode */ + *(volatile ushort *)(PXA_CS4_PHYS + 2) = 0x09; + *(volatile ushort *)(PXA_CS4_PHYS + 0) = 0x90; + *(volatile ushort *)(PXA_CS4_PHYS + 2) = 0x01; + + *(volatile ushort *)(PXA_CS4_PHYS + 2) = 0x05; + *(volatile ushort *)(PXA_CS4_PHYS + 0) = 0x00; + *(volatile ushort *)(PXA_CS4_PHYS + 2) = 0x01; + + makercode = *(volatile ushort *)(PXA_CS4_PHYS + 0x00000000); + devicecode = *(volatile ushort *)(PXA_CS4_PHYS + 0x00000000); + dontcare = *(volatile ushort *)(PXA_CS4_PHYS + 0x00000000); + status2 = *(volatile ushort *)(PXA_CS4_PHYS + 0x00000000); + + *(volatile ushort *)(PXA_CS4_PHYS + 2) = 0x0; + + printf("makercode: %x, devicecode: %x\n", makercode, devicecode); + printf("dontcare: %x, status2: %x\n", dontcare, status2); + + return 0; +} + +int board_late_init(void) +{ + setenv ("stdout","serial"); + setenv ("stdout","serial"); + return 0; +} + +int dram_init( void ){ + DECLARE_GLOBAL_DATA_PTR; + +#if ( CONFIG_NR_DRAM_BANKS > 0 ) + gd->bd->bi_dram[0].start = CFG_SDRAM_1; + gd->bd->bi_dram[0].size = CFG_SDRAM_1_SIZE; +#endif +#if ( CONFIG_NR_DRAM_BANKS > 1 ) + gd->bd->bi_dram[1].start = CFG_SDRAM_2; + gd->bd->bi_dram[1].size = CFG_SDRAM_2_SIZE; +#endif + + return 0; +} + diff --git a/board/scb9520/scb9520.h b/board/scb9520/scb9520.h new file mode 100644 index 0000000..94b6a95 --- /dev/null +++ b/board/scb9520/scb9520.h @@ -0,0 +1,253 @@ +/* + * linux/include/asm-arm/arch-pxa/pcm027.h + * + * (c) 2003 Phytec Messtechnik GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* + * GPIOs Interrupt Source + */ +//#define GPIO_SCB9520_RTC 0 /* GPIO-0 bei Baseboard über GPIO 1 WAKEUP erreichbar */ +#define GPIO_SCB9520_WAKEUP 1 /* GPIO-1 INT-24 */ +#define GPIO_SCB9520_ETH 2 /* GPIO-2 INT-25 */ +#define GPIO_SCB9520_USB_INT1 3 /* GPIO-3 INT-26 */ +#define GPIO_SCB9520_USB_INT2 4 /* GPIO-4 INT-27 */ +#define GPIO_SCB9520_CAN 5 /* GPIO-5 INT-28 */ +#define GPIO_PCM990_CAN0 83 /* GPIO-82 INT-106 */ +#define GPIO_PCM990_CAN1 81 /* GPIO-81 INT-104 */ + +#define GPIO_SCB9520_CTRL_INT 7 /* GPIO-7 INT-30 */ + +#define GPIO_SCB9520_AC97 10 /* GPIO-10 INT-33 */ +#define GPIO_SCB9520_CF 11 /* GPIO-11 INT-34 */ + +#define GPIO_SCB9520_IDE 13 /* GPIO-13 INT-36 */ +#define GPIO_SCB9520_CTRL_PWR 14 /* GPIO-14 INT-37 */ + +/* + * Control PLD Regs + */ + +#define SCB9520_CTRL_PHYS 0x04000000 //16-Bit +#define SCB9520_CTRL_SIZE (1*1024*1024) +#define SCB9520_CTRL_INT_IRQ IRQ_GPIO(GPIO_SCB9520_CTRL_INT) +#define SCB9520_CTRL_PWR_IRQ IRQ_GPIO(GPIO_SCB9520_CTRL_PWR) +#define SCB9520_CTRL_IRQ_EDGE GPIO_FALLING_EDGE + +//#define SCB9520_CTRL_REG0 0x00000000 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0001 /* RESET REGISTER */ ^[C +//#define SCB9520_CTRL_ 0x0002 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0004 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0008 /* RESET REGISTER */ +//#define SCB9520_CTRL_REG1 0x00000002 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0001 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0002 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0004 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0008 /* RESET REGISTER */ +//#define SCB9520_CTRL_REG2 0x00000004 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0001 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0002 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0004 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0008 /* RESET REGISTER */ +#define SCB9520_CTRL_REG3 0x00000006 /* LCD CTRL REGISTER 3 */ +#define SCB9520_CTRL_LCDPWR 0x0001 /* RW LCD Power on */ +#define SCB9520_CTRL_LCDON 0x0002 /* RW LCD Latch on */ +#define SCB9520_CTRL_LCDPOS1 0x0004 /* RW POS 1 */ +#define SCB9520_CTRL_LCDPOS2 0x0008 /* RW POS 2 */ +#define SCB9520_CTRL_REG4 0x00000008 /* MMC1 CTRL REGISTER 4 */ +#define SCB9520_CTRL_MMC1PWR 0x0001 /* RW MMC1 Power on */ +//#define SCB9520_CTRL_ 0x0002 /* R=0 not used */ +//#define SCB9520_CTRL_ 0x0004 /* R=0 not used */ +//#define SCB9520_CTRL_ 0x0008 /* R=0 not used */ +#define SCB9520_CTRL_REG5 0x0000000A /* MMC2 CTRL REGISTER 5 */ +#define SCB9520_CTRL_MMC2PWR 0x0001 /* RW MMC2 Power on */ +#define SCB9520_CTRL_MMC2LED 0x0002 /* RW MMC2 LED */ +#define SCB9520_CTRL_MMC2DE 0x0004 /* R MMC2 Card detect */ +#define SCB9520_CTRL_MMC2WP 0x0008 /* R MMC2 Card write protect */ +//#define SCB9520_CTRL_REG6 0x0000000C /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0001 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0002 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0004 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0008 /* RESET REGISTER */ +//#define SCB9520_CTRL_REG7 0x0000000E /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0001 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0002 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0004 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0008 /* RESET REGISTER */ +//#define SCB9520_CTRL_REG8 0x00000010 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0001 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0002 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0004 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0008 /* RESET REGISTER */ +//#define SCB9520_CTRL_REG9 0x00000012 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0001 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0002 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0004 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0008 /* RESET REGISTER */ +//#define SCB9520_CTRL_REG10 0x00000014 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0001 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0002 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0004 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0008 /* RESET REGISTER */ +//#define SCB9520_CTRL_REG11 0x00000016 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0001 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0002 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0004 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0008 /* RESET REGISTER */ +//#define SCB9520_CTRL_REG12 0x00000018 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0001 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0002 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0004 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0008 /* RESET REGISTER */ +//#define SCB9520_CTRL_REG13 0x0000001A /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0001 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0002 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0004 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0008 /* RESET REGISTER */ +//#define SCB9520_CTRL_REG14 0x0000001C /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0001 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0002 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0004 /* RESET REGISTER */ +//#define SCB9520_CTRL_ 0x0008 /* RESET REGISTER */ +//#define SCB9520_CTRL_REG15 0x0000001E /* RESET REGISTER */ + + +#define __SCB9520_CTRL_REG(x) (*((volatile unsigned char *)(x))) + +/* + * IDE + */ + +#define SCB9520_IDE_IRQ IRQ_GPIO(GPIO_SCB9520_IDE) +#define SCB9520_IDE_IRQ_EDGE GPIO_RISING_EDGE + +#define SCB9520_IDE_PLD_PHYS 0x20000000 /* 16-Bit Zugriff */ +#define SCB9520_IDE_PLD_BASE 0xf6000000 +#define SCB9520_IDE_PLD_SIZE (1*1024*1024) + +#define SCB9520_IDE_PLD_REG0 0x00001000 /* OFFSET IDE REGISTER 0 */ +/*#define SCB9520_IDE_ 0x0001*/ /* R=0 not used */ +/*#define SCB9520_IDE_ 0x0002*/ /* R=0 not used */ +#define SCB9520_IDE_PM5V 0x0004 /* R System VCC_5V */ +#define SCB9520_IDE_STBY 0x0008 /* R System StandBy */ + +#define SCB9520_IDE_PLD_REG1 0x00001002 /* OFFSET IDE REGISTER 1 */ +#define SCB9520_IDE_IDEMODE 0x0001 /* R TrueIDE Mode */ +/*#define SCB9520_IDE_ 0x0002*/ /* R=0 not used */ +#define SCB9520_IDE_DMAENA 0x0004 /* RW DMA Enable */ +#define SCB9520_IDE_DMA1_0 0x0008 /* RW 1=DREQ1 0=DREQ0 */ + +#define SCB9520_IDE_PLD_REG2 0x00001004 /* OFFSET IDE REGISTER 2 */ +#define SCB9520_IDE_RESENA 0x0001 /* RW IDE Reset Bit enable */ +#define SCB9520_IDE_RES 0x0002 /* RW IDE Reset Bit */ +/*#define SCB9520_IDE_ 0x0004*/ /* R=0 */ +#define SCB9520_IDE_RDY 0x0008 /* RDY */ + +#define SCB9520_IDE_PLD_REG3 0x00001006 /* OFFSET IDE REGISTER 3 */ +#define SCB9520_IDE_IDEOE 0x0001 /* RW Latch on Databus */ +#define SCB9520_IDE_IDEON 0x0002 /* RW Latch on Control Address */ +#define SCB9520_IDE_IDEIN 0x0004 /* RW Latch on Interrupt usw. */ +/*#define SCB9520_IDE_ 0x0008*/ /* R=0 not used */ + +#define SCB9520_IDE_PLD_REG4 0x00001008 /* OFFSET IDE REGISTER 4 */ +#define SCB9520_IDE_PWRENA 0x0001 /* RW IDE Power enable */ +#define SCB9520_IDE_5V 0x0002 /* R IDE Power 5V */ +/*#define SCB9520_IDE_ 0x0004*/ /* R=0 not used */ +#define SCB9520_IDE_PWG 0x0008 /* R IDE Power is on */ + +/*#define SCB9520_IDE_PLD_REG5 0x0000100E*/ /* OFFSET IDE REGISTER 5 */ +/*#define SCB9520_IDE_REG5_ 0x0004*/ /* R=0 not used */ +/*#define SCB9520_IDE_REG5_ 0x0008*/ /* R=0 not used */ +/*#define SCB9520_IDE_REG5_ 0x0004*/ /* R=0 not used */ +/*#define SCB9520_IDE_REG5_ 0x0008*/ /* R=0 not used */ + +/*#define SCB9520_IDE_PLD_REG6 0x00001010*/ /* OFFSET IDE REGISTER 6 */ +/*#define SCB9520_IDE_REG6_ 0x0004*/ /* R=0 not used */ +/*#define SCB9520_IDE_REG6_ 0x0008*/ /* R=0 not used */ +/*#define SCB9520_IDE_REG6_ 0x0004*/ /* R=0 not used */ +/*#define SCB9520_IDE_REG6_ 0x0008*/ /* R=0 not used */ + +/*#define SCB9520_IDE_PLD_REG7 0x00001012*/ /* OFFSET IDE REGISTER 7 */ +/*#define SCB9520_IDE_REG7_ 0x0004*/ /* R=0 not used */ +/*#define SCB9520_IDE_REG7_ 0x0008*/ /* R=0 not used */ +/*#define SCB9520_IDE_REG7_ 0x0004*/ /* R=0 not used */ +/*#define SCB9520_IDE_REG7_ 0x0008*/ /* R=0 not used */ + + +#define __SCB9520_IDE_PLD_REG(x) (*((volatile unsigned char *)(x))) + +/* + * Compact Flash + */ +#define SCB9520_CF_IRQ IRQ_GPIO(GPIO_SCB9520_CF) +#define SCB9520_CF_IRQ_EDGE GPIO_RISING_EDGE + + +#define SCB9520_CF_PLD_PHYS 0x30001000 //16-Bit +#define SCB9520_CF_PLD_SIZE (1*1024*1024) + +#define SCB9520_CF_PLD_REG0 0x00000000 /* OFFSET CF REGISTER 0 */ +#define SCB9520_CF_REG0_LED 0x0001 /* RW LED an */ +#define SCB9520_CF_REG0_BLK 0x0002 /* RW LED Blink bei Zugriff */ +#define SCB9520_CF_REG0_PM5V 0x0004 /* R System VCC_5V an */ +#define SCB9520_CF_REG0_STBY 0x0008 /* R System StandBy */ + +#define SCB9520_CF_PLD_REG1 0x00000002 /* OFFSET CF REGISTER 1 */ +#define SCB9520_CF_REG1_IDEMODE 0x0001 /* RW CF-Card als TrueIDE */ +#define SCB9520_CF_REG1_CF0 0x0002 /* RW CF-Card auf ADDR 0x28000000 */ +/*#define SCB9520_CF_REG1_ 0x0004*/ /* R=0 not used */ +/*#define SCB9520_CF_REG1_ 0x0008*/ /* R=0 not used */ + +#define SCB9520_CF_PLD_REG2 0x00000004 /* OFFSET CF REGISTER 2 */ +#define SCB9520_CF_REG2_RESENA 0x0001 /* RW CF RESET BIT Enable */ +#define SCB9520_CF_REG2_RES 0x0002 /* RW CF RESET BIT */ +#define SCB9520_CF_REG2_RDYENA 0x0004 /* RW Enabele CF_RDY */ +#define SCB9520_CF_REG2_RDY 0x0008 /* R CF_RDY auf PWAIT */ + +#define SCB9520_CF_PLD_REG3 0x00000006 /* OFFSET CF REGISTER 3 */ +#define SCB9520_CF_REG3_CFOE 0x0001 /* RW Latch on Databus */ +#define SCB9520_CF_REG3_CFON 0x0002 /* RW Latch on Control Address */ +#define SCB9520_CF_REG3_CFIN 0x0004 /* RW Latch on Interrupt usw. */ +#define SCB9520_CF_REG3_CFCD 0x0008 /* RW Latch on CD1/2 VS1/2 usw */ + +#define SCB9520_CF_PLD_REG4 0x00000008 /* OFFSET CF REGISTER 4 */ +#define SCB9520_CF_REG4_PWRENA 0x0001 /* RW CF Power on (CD1/2 = "00") */ +#define SCB9520_CF_REG4_5_3V 0x0002 /* RW 1 = 5V CF_VCC 0 = 3 V CF_VCC */ +#define SCB9520_CF_REG4_3B 0x0004 /* RW 3.0V Backup aus VCC (5_3V=0) */ +#define SCB9520_CF_REG4_PWG 0x0008 /* R CF-Power is on */ + +#define SCB9520_CF_PLD_REG5 0x0000000A /* OFFSET CF REGISTER 5 */ +#define SCB9520_CF_REG5_BVD1 0x0001 /* R CF /BVD1 */ +#define SCB9520_CF_REG5_BVD2 0x0002 /* R CF /BVD2 */ +#define SCB9520_CF_REG5_VS1 0x0004 /* R CF /VS1 */ +#define SCB9520_CF_REG5_VS2 0x0008 /* R CF /VS2 */ + +#define SCB9520_CF_PLD_REG6 0x0000000C /* OFFSET CF REGISTER 6 */ +#define SCB9520_CF_REG6_CD1 0x0001 /* R CF Card_Detect1 */ +#define SCB9520_CF_REG6_CD2 0x0002 /* R CF Card_Detect2 */ +/*#define SCB9520_CF_REG1_ 0x0004*/ /* R=0 not used */ +/*#define SCB9520_CF_REG1_ 0x0008*/ /* R=0 not used */ + +/*#define SCB9520_CF_PLD_REG7 0x0000000E*/ /* OFFSET CF REGISTER 7 */ +/*#define SCB9520_CF_REG7_ 0x0004*/ /* R=0 not used */ +/*#define SCB9520_CF_REG7_ 0x0008*/ /* R=0 not used */ +/*#define SCB9520_CF_REG7_ 0x0004*/ /* R=0 not used */ +/*#define SCB9520_CF_REG7_ 0x0008*/ /* R=0 not used */ + + +#define __SCB9520_CF_PLD_REG(x) (*((volatile unsigned char *)(x))) + diff --git a/board/scb9520/u-boot.lds b/board/scb9520/u-boot.lds new file mode 100644 index 0000000..f010239 --- /dev/null +++ b/board/scb9520/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/common/Makefile b/common/Makefile index 0106088..75b8749 100644 --- a/common/Makefile +++ b/common/Makefile @@ -31,6 +31,7 @@ COBJS = main.o ACEX1K.o altera.o bedbug.o circbuf.o \ cmd_ace.o cmd_autoscript.o \ cmd_bdinfo.o cmd_bedbug.o cmd_bmp.o cmd_boot.o cmd_bootm.o \ cmd_cache.o cmd_console.o \ + cmd_burst.o cmd_pme.o \ cmd_date.o cmd_dcr.o cmd_diag.o cmd_display.o cmd_doc.o cmd_dtt.o \ cmd_eeprom.o cmd_elf.o cmd_ext2.o \ cmd_fat.o cmd_fdc.o cmd_fdos.o cmd_flash.o cmd_fpga.o \ diff --git a/common/cmd_burst.c b/common/cmd_burst.c new file mode 100644 index 0000000..c5cb933 --- /dev/null +++ b/common/cmd_burst.c @@ -0,0 +1,177 @@ +/* + * Enable Sync Burst Mode on scb9328 Boards + */ +#include +#include + +#if defined(CONFIG_SCB9328) + +#include +#include + +#ifdef CONFIG_IMX_DBG +#define debug_imx(fmt,args...) printf (fmt ,##args) +#define debugX_imx(level,fmt,args...) if (DEBUG>=level) printf(fmt,##args); +#else +#define debug_imx(fmt,args...) +#define debugX_imx(level,fmt,args...) +#endif /* DEBUG */ + +#define FLASH_BUS vu_short + +extern flash_info_t flash_info[]; /* info for FLASH chips */ + +// K FIXME static int on_off (const char *); +static int do_burst (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +static int burst_on_off (const char *); +static int burst_status (void); +static void print_ids (void); +static int get_vals (void); + +void burst_disable (void); +int burst_enable (void); + +/* -------------------------------------------------------------------- */ + +static int do_burst (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + switch (argc) { + case 2: /* on / off */ + switch (burst_on_off(argv[1])) { + case 0: burst_disable (); + break; + case 1: burst_enable (); + break; + } + /* FALL TROUGH */ + case 1: /* get status */ + printf ("Burst Mode CS0 is %s\n", + burst_status() ? "ON" : "OFF"); + return 0; + default: + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + return 0; +} + +static int burst_on_off (const char *s) +{ + if (strcmp(s, "on") == 0) { + return (1); + } else if (strcmp(s, "off") == 0) { + return (0); + } + return (-1); +} + +static int burst_status () +{ + + if ( __REG(IMX_EIM_BASE) & 1<<20 ) { + debug_imx("SYNC Bit set, "); + if ( __REG(IMX_EIM_BASE) & 1<<21) { + debug_imx("PME active\n"); + return 0; + } else { + debug_imx("Sync Burst Mode ON\n"); + return 1; + } + } else { + return 0; + } + +} + +static void print_ids () +{ + flash_info_t *info; + info = &flash_info[0]; + debug_imx("info->device_id: 0x%08lx\n", info->device_id); + debug_imx("info->manufacturer_id: 0x%08lx\n", info->manufacturer_id); +} + +void burst_disable () +{ + int moddedrcr; + flash_info_t *info; + info = &flash_info[0]; + + print_ids(); + + moddedrcr = (info->rcr_val | (2*0x8000)); + + debug_imx("info->rcr_val : 0x%08lx\n", info->rcr_val); + debug_imx("info->rcr_val modded: 0x%08lx\n", moddedrcr); + + *((FLASH_BUS *) moddedrcr) = FLASH_RCR_CMD; + *((FLASH_BUS *) moddedrcr) = FLASH_ACK_CMD; + __REG(IMX_EIM_BASE) = CFG_CS0U_VAL; +} + +static int get_vals () +{ + flash_info_t *info; + info = &flash_info[0]; + + print_ids(); + + switch (info->manufacturer_id) { + case 0x89: + debug_imx("This is intel, looking up device_id\n"); + switch (info->device_id) { + case 0x8801: case 0x8802: case 0x8803: /* 64, 128, 256 Mbit K3 */ + printf("intel K3 device found, setting up...\n"); + info->rcr_val = K3_RCR_B_VAL; + info->cs0u_val = K3_CS0U_B_VAL; + break; + case 0x8817: case 0x8818: case 0x8919: case 0x8922: case 0x881a: case 0x881b: case 0x891c: /* P30 */ + printf("intel P30 device found, setting up...\n"); + info->rcr_val = K3_RCR_B_VAL; + info->cs0u_val = K3_CS0U_B_VAL; + break; + case 0x0016: case 0x0017: case 0x0018: + printf("intel J3 device found, burst mode not available...\n"); + break; + default: + debug_imx("NOT enabling burst mode, unknown device id\n"); + break; + } + break; + default: + debug_imx("NOT enabling burst mode, unknown vendor id\n"); + info->rcr_val = 0x0; + info->cs0u_val = 0x0; + break; + } + debug_imx("info->rcr_val: 0x%08lx\n", info->rcr_val); +} + +int burst_enable () +{ + + flash_info_t *info; + info = &flash_info[0]; + + get_vals(); + + if (info->rcr_val == 0 || info->cs0u_val == 0) { + debug_imx("rcr_val or cs0_val bogus, exiting\n"); + return 0; + } else { + debug_imx("enabling intel sync burst mode\n"); + *((FLASH_BUS *) info->rcr_val) = FLASH_RCR_CMD; + *((FLASH_BUS *) info->rcr_val) = FLASH_ACK_CMD; + __REG(IMX_EIM_BASE) = info->cs0u_val; + } + return 0; +} + +U_BOOT_CMD( + burst, 2, 1, do_burst, + "burst - enable or disable sync burst mode\n", + "[on, off]\n" + " - enable or disable sync burst mode\n" + ); + +#endif /* CONFIG_SCB9328 */ diff --git a/common/cmd_flash.c b/common/cmd_flash.c index cb1c5bb..ebdbbe8 100644 --- a/common/cmd_flash.c +++ b/common/cmd_flash.c @@ -477,6 +477,9 @@ int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) addr_last = simple_strtoul(argv[3], NULL, 16); if (addr_dataflash(addr_first) && addr_dataflash(addr_last)) { + printf("\n flash_sect_protect called with \n"); + printf("addr_first: %i 0x%08lx and addr_last: %i 0x%08lx and p: %i\n", + addr_first, addr_first, addr_last, addr_last, i); status = dataflash_real_protect(p,addr_first,addr_last); if (status < 0){ puts ("Bad DataFlash sector specification\n"); @@ -690,7 +693,7 @@ U_BOOT_CMD( ); U_BOOT_CMD( - erase, 3, 1, do_flerase, + erase, 3, 0, do_flerase, "erase - erase FLASH memory\n", "start end\n" " - erase FLASH from addr 'start' to addr 'end'\n" diff --git a/common/cmd_net.c b/common/cmd_net.c index 2cb2c5d..7534d2b 100644 --- a/common/cmd_net.c +++ b/common/cmd_net.c @@ -151,12 +151,17 @@ static void netboot_update_env (void) #endif } +#ifndef CFG_DIRECT_FLASH_TFTP +extern flash_info_t flash_info[]; +#endif + static int netboot_common (proto_t proto, cmd_tbl_t *cmdtp, int argc, char *argv[]) { char *s; int rcode = 0; int size; + int i; /* pre-set load_addr */ if ((s = getenv("loadaddr")) != NULL) { @@ -187,6 +192,17 @@ netboot_common (proto_t proto, cmd_tbl_t *cmdtp, int argc, char *argv[]) return 1; } +#ifndef CFG_DIRECT_FLASH_TFTP + for (i=0; i= flash_info[i].start[0] && + load_addr < flash_info[i].start[0] + flash_info[i].size) { + printf("load address is in flash. Will not overwrite\n"); + return 1; + } + } +#endif + if ((size = NetLoop(proto)) < 0) return 1; diff --git a/common/cmd_pme.c b/common/cmd_pme.c new file mode 100644 index 0000000..ca7e660 --- /dev/null +++ b/common/cmd_pme.c @@ -0,0 +1,228 @@ +/* + * Enable PME mode on scb9328 Boards + */ +#include +#include + +#if defined(CONFIG_SCB9328) + +#include +#include + +#ifdef CONFIG_IMX_DBG +#define debug_imx(fmt,args...) printf (fmt ,##args) +#define debugX_imx(level,fmt,args...) if (DEBUG>=level) printf(fmt,##args); +#else +#define debug_imx(fmt,args...) +#define debugX_imx(level,fmt,args...) +#endif + +#define FLASH_BUS vu_short + +extern flash_info_t flash_info[]; + +static int do_pme (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +static int pme_on_off (const char *); +static int pme_status (void); +static void pme_print_ids (void); +static int pme_get_vals (void); +int pme_on (void); +void pme_off (void); + +static int do_pme (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + switch (argc) { + case 2: + switch (pme_on_off(argv[1])) { + case 0: pme_off(); + break; + case 1: pme_on(); + break; + } + break; + case 1: + printf ("PME CS0 is %s\n", pme_status() ? "ON" : "OFF"); + return 1; + break; + } + return 0; +} + +static int pme_on_off (const char *s) +{ + if (strcmp(s, "on") == 0) { + return (1); + } else if (strcmp(s, "off") == 0) { + return (0); + } + return (-1); +} + +static int pme_status () +{ + if ( __REG(IMX_EIM_BASE) & 1<<21) { + return 1; + } else { + return 0; + } +} + +static void pme_print_ids () +{ + flash_info_t *info; + info = &flash_info[0]; + debug_imx("info->manufacturer_id: 0x%08lx\n", info->manufacturer_id); + debug_imx("info->device_id: 0x%08lx\n", info->device_id); +} + +void pme_off () +{ + flash_info_t *info; + info = &flash_info[0]; + + pme_print_ids(); + + switch (info->manufacturer_id) { + case 0x89: + debug_imx("This is intel, looking up device_id\n"); + switch (info->device_id) { + case 0x8801: case 0x8802: case 0x8803: /* 64, 128, 256 Mbit K3 */ + printf("intel K3 found, restoring failsafe settings...\n"); + __REG(IMX_EIM_BASE) = CFG_CS0U_VAL; + info->cs0l_val = (K3_CS0L_P_VAL & ~CS0L_DSZ_MASK) + | (__REG(IMX_EIM_BASE+0x4) & CS0L_DSZ_MASK); + __REG(IMX_EIM_BASE+0x4) = info->cs0l_val; + break; + case 0x8817: case 0x8818: case 0x8919: case 0x8922: case 0x881a: case 0x881b: case 0x891c: /* P30 */ + printf("intel P30 found, restoring failsafe settings...\n"); + + printf("CS0L 0x%x\n", __REG(IMX_EIM_BASE+0x4)); + + __REG(IMX_EIM_BASE) = CFG_CS0U_VAL; + info->cs0l_val = (P30_CS0L_P_VAL & ~CS0L_DSZ_MASK) + | (__REG(IMX_EIM_BASE+0x4) & CS0L_DSZ_MASK); + __REG(IMX_EIM_BASE+0x4) = info->cs0l_val; + break; + case 0x0016: case 0x0017: case 0x0018: + printf("intel J3 found, restoring failsafe settings...\n"); + *((FLASH_BUS *) J3_RCR_V_VAL) = FLASH_RCR_CMD; + *((FLASH_BUS *) J3_RCR_V_VAL) = FLASH_J3_ACK_CMD; + __REG(IMX_EIM_BASE) = CFG_CS0U_VAL; + info->cs0l_val = (J3_CS0L_P_VAL & ~CS0L_DSZ_MASK) + | (__REG(IMX_EIM_BASE+0x4) & CS0L_DSZ_MASK); + __REG(IMX_EIM_BASE+0x4) = info->cs0l_val; + break; + default: + debug_imx("NOT disabling PME mode, unknown device id\n"); + break; + } + break; + default: + debug_imx("NOT disabling PME mode, unknown vendor id\n"); + break; + } +} + +static int pme_get_vals () +{ + flash_info_t *info; + info = &flash_info[0]; + + pme_print_ids(); + + switch (info->manufacturer_id) { + case 0x89: + debug_imx("This is intel, looking up device_id\n"); + switch (info->device_id) { + case 0x8801: case 0x8802: case 0x8803: /* 64, 128, 256 Mbit K3 */ + printf("intel K3 found, setting up...\n"); + info->rcr_val = 0x0; + info->cs0u_val = K3_CS0U_P_VAL; + info->cs0l_val = (K3_CS0L_P_VAL & ~CS0L_DSZ_MASK) + | (__REG(IMX_EIM_BASE+0x4) & CS0L_DSZ_MASK); + debug_imx("unlocking this beast...\n"); + break; + case 0x8817: case 0x8818: case 0x8919: case 0x8922: case 0x881a: case 0x881b: case 0x891c: /* P30 */ + printf("intel P30 found, setting up......\n"); + info->rcr_val = 0x0; + info->cs0u_val = P30_CS0U_P_VAL; + info->cs0l_val = (P30_CS0L_P_VAL & ~CS0L_DSZ_MASK) + | (__REG(IMX_EIM_BASE+0x4) & CS0L_DSZ_MASK); + debug_imx("unlocking this beast...\n"); + break; + case 0x0016: case 0x0017: case 0x0018: + printf("intel J3 found...\n"); + info->rcr_val = J3_RCR_P_VAL; + info->cs0u_val = J3_CS0U_P_VAL; + info->cs0l_val = (J3_CS0L_P_VAL & ~CS0L_DSZ_MASK) + | (__REG(IMX_EIM_BASE+0x4) & CS0L_DSZ_MASK); + break; + default: + debug_imx("NOT enabling PME mode, unknown device id\n"); + break; + } + break; + default: + debug_imx("NOT enabling PME mode, unknown vendor id\n"); + info->rcr_val = 0x0; + info->cs0u_val = 0x0; + break; + } + debug_imx("info->rcr_val: 0x%08lx\n", info->rcr_val); +} + +int pme_on () +{ + flash_info_t *info; + info = &flash_info[0]; + int i; + + pme_get_vals(); + + if ( info->rcr_val == 0 && info->cs0u_val == 0) { + debug_imx("rcr_val or cs0u_val bogus, exiting\n"); + return 0; + } else { + debug_imx("enabling intel PME mode\n"); + switch (info->device_id) { + case 0x8801: case 0x8802: case 0x8803: /* 64, 128, 256 Mbit K3 */ + printf("intel K3 found, enabling PME...\n"); + __REG(IMX_EIM_BASE) = info->cs0u_val; + __REG(IMX_EIM_BASE+0x4) = info->cs0l_val; + debug_imx("unlocking all but first 2 sectors...\n"); + for (i = 2; i < info->sector_count; i++) { + flash_real_protect(info, i, 0); + } + break; + case 0x8817: case 0x8818: case 0x8919: case 0x8922: case 0x881a: case 0x881b: case 0x891c: /* P30 */ + printf("intel P30 found, enabling PME...\n"); + __REG(IMX_EIM_BASE) = info->cs0u_val; + __REG(IMX_EIM_BASE+0x4) = info->cs0l_val; + debug_imx("unlocking all but first 2 sectors...\n"); + for (i = 2; i < info->sector_count; i++) { + flash_real_protect(info, i, 0); + } + break; + case 0x0016: case 0x0017: case 0x0018: + printf("intel J3 found, enabling PME...\n"); + *((FLASH_BUS *) info->rcr_val) = FLASH_RCR_CMD; + *((FLASH_BUS *) info->rcr_val) = FLASH_J3_ACK_CMD; + __REG(IMX_EIM_BASE) = info->cs0u_val; + __REG(IMX_EIM_BASE+0x4) = info->cs0l_val; + break; + default: + debug_imx("NOT enabling PME mode, unknown device id\n"); + break; + } + return 0; + } +} + +U_BOOT_CMD( + pme, 2, 1, do_pme, + "pme - read vendor/device id, enable pme mode\n", + "[on, off]\n" + " - read vendor/device id, enable pme mode\n" + ); + +#endif /* CONFIG_SCB9328 */ diff --git a/cpu/arm920t/config.mk b/cpu/arm920t/config.mk index 8db4adb..fc54845 100644 --- a/cpu/arm920t/config.mk +++ b/cpu/arm920t/config.mk @@ -30,5 +30,5 @@ PLATFORM_CPPFLAGS += -march=armv4 # Supply options according to compiler version # # ========================================================================= -PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) +PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32) PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/cpu/arm920t/cpu.c b/cpu/arm920t/cpu.c index f93bf57..7bec77c 100644 --- a/cpu/arm920t/cpu.c +++ b/cpu/arm920t/cpu.c @@ -128,6 +128,10 @@ int cleanup_before_linux (void) int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { +#ifdef CONFIG_SCB9328_SNCBRST + extern int burst_status (void); + burst_disable(); +#endif disable_interrupts (); reset_cpu (0); /*NOTREACHED*/ diff --git a/cpu/arm920t/imx/interrupts.c b/cpu/arm920t/imx/interrupts.c index 03ce06d..4a4be7f 100644 --- a/cpu/arm920t/imx/interrupts.c +++ b/cpu/arm920t/imx/interrupts.c @@ -60,7 +60,7 @@ void reset_timer (void) ulong get_timer (ulong base) { - return get_timer_masked (); + return get_timer_masked () - base; } void set_timer (ulong t) diff --git a/cpu/arm920t/imx/speed.c b/cpu/arm920t/imx/speed.c index 1e29698..8a0e6c7 100644 --- a/cpu/arm920t/imx/speed.c +++ b/cpu/arm920t/imx/speed.c @@ -42,8 +42,8 @@ ulong get_systemPLLCLK(void) /* FIXME: We assume System_SEL = 0 here */ u32 spctl0 = SPCTL0; u32 mfi = (spctl0 >> 10) & 0xf; - u32 mfn = spctl0 & 0x3f; - u32 mfd = (spctl0 >> 16) & 0x3f; + u32 mfn = spctl0 & 0x3ff; + u32 mfd = (spctl0 >> 16) & 0x3ff; u32 pd = (spctl0 >> 26) & 0xf; mfi = mfi<=5 ? 5 : mfi; @@ -51,18 +51,20 @@ ulong get_systemPLLCLK(void) return (2*(CONFIG_SYSPLL_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1); } +#if defined (CONFIG_IMX_DBG) + ulong get_mcuPLLCLK(void) { /* FIXME: We assume System_SEL = 0 here */ u32 mpctl0 = MPCTL0; u32 mfi = (mpctl0 >> 10) & 0xf; - u32 mfn = mpctl0 & 0x3f; - u32 mfd = (mpctl0 >> 16) & 0x3f; + u32 mfn = mpctl0 & 0x3ff; + u32 mfd = (mpctl0 >> 16) & 0x3ff; u32 pd = (mpctl0 >> 26) & 0xf; mfi = mfi<=5 ? 5 : mfi; - return (2*(CONFIG_SYS_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1); + return (2*(CONFIG_MPLL_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1); } ulong get_FCLK(void) @@ -74,7 +76,6 @@ ulong get_FCLK(void) ulong get_HCLK(void) { u32 bclkdiv = (( CSCR >> 10 ) & 0xf) + 1; - printf("bclkdiv: %d\n", bclkdiv); return get_systemPLLCLK() / bclkdiv; } @@ -84,11 +85,6 @@ ulong get_BCLK(void) return get_HCLK(); } -ulong get_PERCLK1(void) -{ - return get_systemPLLCLK() / (((PCDR) & 0xf)+1); -} - ulong get_PERCLK2(void) { return get_systemPLLCLK() / (((PCDR>>4) & 0xf)+1); @@ -99,4 +95,11 @@ ulong get_PERCLK3(void) return get_systemPLLCLK() / (((PCDR>>16) & 0x7f)+1); } +#endif /* defined (CONFIG_IMX_DBG) */ + +ulong get_PERCLK1(void) +{ + return get_systemPLLCLK() / (((PCDR) & 0xf)+1); +} + #endif /* defined (CONFIG_IMX) */ diff --git a/cpu/pxa/i2c.c b/cpu/pxa/i2c.c index 722d949..d6f6493 100644 --- a/cpu/pxa/i2c.c +++ b/cpu/pxa/i2c.c @@ -45,6 +45,7 @@ #include #include +#define DEBUG_I2C 1 /*#define DEBUG_I2C 1 /###* activate local debugging output */ #define I2C_PXA_SLAVE_ADDR 0x1 /* slave pxa unit address */ diff --git a/cpu/pxa/pxafb.c b/cpu/pxa/pxafb.c index b2caa73..6d006f8 100644 --- a/cpu/pxa/pxafb.c +++ b/cpu/pxa/pxafb.c @@ -147,6 +147,38 @@ vidinfo_t panel_info = { #endif /* CONFIG_HITACHI_SX14 */ /*----------------------------------------------------------------------*/ +#ifdef CONFIG_SHARP_LQ084V1DG21 + +# define LCD_BPP LCD_COLOR8 +# define LCD_INVERT_COLORS /* Needed for colors to be correct, but why? */ + +/* you have to set lccr0 and lccr3 (including pcd) */ +# define REG_LCCR0 0x003008F9 +# define REG_LCCR3 0x03700001 + +vidinfo_t panel_info = { + vl_col: 640, + vl_row: 480, + vl_width: 171, + vl_height: 130, + vl_clkp: CFG_LOW, + vl_oep: CFG_HIGH, + vl_hsp: CFG_LOW, + vl_vsp: CFG_LOW, + vl_dp: CFG_HIGH, /* not used by PXA */ + vl_bpix: LCD_BPP, + vl_lbw: 1, + vl_splt: 0, + vl_clor: 1, + vl_tft: 1, + vl_hpw: 20, + vl_blw: 103, + vl_elw: 47, + vl_vpw: 6, + vl_bfw: 28, + vl_efw: 5, +}; +#endif /* CONFIG_SHARP_LQ084V1DG21 */ #if LCD_BPP == LCD_COLOR8 void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue); diff --git a/cpu/pxa/serial.c b/cpu/pxa/serial.c index cb3a478..09e036d 100644 --- a/cpu/pxa/serial.c +++ b/cpu/pxa/serial.c @@ -61,7 +61,7 @@ void serial_setbrg (void) #endif /* CONFIG_CPU_MONAHANS */ FFIER = 0; /* Disable for now */ - FFFCR = 0; /* No fifos enabled */ + FFFCR = FCR_TRFIFOE; /* Fifos enabled */ /* set baud rate */ FFLCR = LCR_WLS0 | LCR_WLS1 | LCR_DLAB; @@ -79,7 +79,7 @@ void serial_setbrg (void) #endif /* CONFIG_CPU_MONAHANS */ BTIER = 0; - BTFCR = 0; + BTFCR = FCR_TRFIFOE; /* Fifos enabled */ /* set baud rate */ BTLCR = LCR_DLAB; diff --git a/drivers/cfi_flash.c b/drivers/cfi_flash.c index 2699cce..433772b 100644 --- a/drivers/cfi_flash.c +++ b/drivers/cfi_flash.c @@ -977,6 +977,14 @@ static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect) flash_write_cmd (info, sect, AMD_ADDR_ACK, AMD_CMD_UNLOCK_ACK); } +static int flash_ven_dev (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd) +{ + cfiword_t cword; + flash_make_cmd (info, cmd, &cword); + info->manufacturer_id = *(volatile u16 *) CFG_FLASH_BASE; + info->device_id = *(volatile u16 *) (CFG_FLASH_BASE + 2); +} + /*----------------------------------------------------------------------- */ static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd) @@ -1214,6 +1222,8 @@ ulong flash_get_size (ulong base, int banknum) #ifdef DEBUG flash_printqry (info, 0); #endif + flash_ven_dev (info, 0, 0, 0x90); + switch (info->vendor) { case CFI_CMDSET_INTEL_STANDARD: case CFI_CMDSET_INTEL_EXTENDED: diff --git a/include/asm-arm/arch-imx/imx-regs.h b/include/asm-arm/arch-imx/imx-regs.h index 318de22..882f30d 100644 --- a/include/asm-arm/arch-imx/imx-regs.h +++ b/include/asm-arm/arch-imx/imx-regs.h @@ -8,9 +8,7 @@ # ifndef __ASSEMBLY__ # define __REG(x) (*((volatile u32 *)(x))) -# define __REG2(x,y) \ - ( __builtin_constant_p(y) ? (__REG((x) + (y))) \ - : (*(volatile u32 *)((u32)&__REG(x) + (y))) ) +# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y))) # else # define __REG(x) (x) # define __REG2(x,y) ((x)+(y)) @@ -218,8 +216,8 @@ #define PB27_PF_USBD_VMO ( GPIO_PORTB | GPIO_PF | 27 ) #define PB28_PF_UART2_CTS ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 ) #define PB29_PF_UART2_RTS ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 ) -#define PB30_PF_UART2_TXD ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 ) -#define PB31_PF_UART2_RXD ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 ) +#define PB30_PF_UART2_TXD ( GPIO_PORTB | GPIO_OUT | GPIO_PF | GPIO_PUEN | 30 ) +#define PB31_PF_UART2_RXD ( GPIO_PORTB | GPIO_IN | GPIO_PF | GPIO_PUEN | 31 ) #define PC3_PF_SSI_RXFS ( GPIO_PORTC | GPIO_PF | 3 ) #define PC4_PF_SSI_RXCLK ( GPIO_PORTC | GPIO_PF | 4 ) #define PC5_PF_SSI_RXDAT ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 ) @@ -228,8 +226,8 @@ #define PC8_PF_SSI_TXCLK ( GPIO_PORTC | GPIO_PF | 8 ) #define PC9_PF_UART1_CTS ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 ) #define PC10_PF_UART1_RTS ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 ) -#define PC11_PF_UART1_TXD ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 ) -#define PC12_PF_UART1_RXD ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 ) +#define PC11_PF_UART1_TXD ( GPIO_PORTC | GPIO_OUT | GPIO_PF | GPIO_PUEN | 11 ) +#define PC12_PF_UART1_RXD ( GPIO_PORTC | GPIO_IN | GPIO_PF | GPIO_PUEN | 12 ) #define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 ) #define PC14_PF_SPI1_SCLK ( GPIO_PORTC | GPIO_PF | 14 ) #define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 ) diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index ebda719..2594082 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -1269,15 +1269,15 @@ typedef void (*ExcpHndlr) (void) ; #define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) #define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) -#define GPLR(x) ((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3) -#define GPDR(x) ((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3) -#define GPSR(x) ((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3) -#define GPCR(x) ((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3) -#define GRER(x) ((((x) & 0x7f) < 96) ? _GRER(x) : GRER3) -#define GFER(x) ((((x) & 0x7f) < 96) ? _GFER(x) : GFER3) -#define GEDR(x) ((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3) -#define GAFR(x) ((((x) & 0x7f) < 96) ? _GAFR(x) : \ - ((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U)) +#define GPLR(x) (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3)) +#define GPDR(x) (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3)) +#define GPSR(x) (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3)) +#define GPCR(x) (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3)) +#define GRER(x) (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3)) +#define GFER(x) (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3)) +#define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3)) +#define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \ + ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U))) #else #define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) @@ -2168,6 +2168,11 @@ typedef void (*ExcpHndlr) (void) ; #define MCIO0_OFFSET 0x38 #define MCIO1_OFFSET 0x3C #define MDMRS_OFFSET 0x40 +#define BSCNTR0_OFFSET 0x4C +#define BSCNTR1_OFFSET 0x50 +#define BSCNTR2_OFFSET 0x5C +#define BSCNTR3_OFFSET 0x60 +#define MDMRSLP_OFFSET 0x58 #define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */ #define MDCNFG_DE0 0x00000001 diff --git a/include/asm-arm/global_data.h b/include/asm-arm/global_data.h index c2d5291..d47c004 100644 --- a/include/asm-arm/global_data.h +++ b/include/asm-arm/global_data.h @@ -61,6 +61,6 @@ typedef struct global_data { #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ #define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r8") +#define DECLARE_GLOBAL_DATA_PTR register gd_t *volatile gd asm ("r8") #endif /* __ASM_GBL_DATA_H */ diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h index 7d7888e..938a8c8 100644 --- a/include/asm-arm/mach-types.h +++ b/include/asm-arm/mach-types.h @@ -737,6 +737,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_CB3RUFC 726 #define MACH_TYPE_MP2USB 727 #define MACH_TYPE_PDNB3 1002 +#define MACH_TYPE_SCB9520 1288 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -6798,6 +6799,18 @@ extern unsigned int __machine_arch_type; # define machine_is_scb9328() (0) #endif +#ifdef CONFIG_MACH_SCB9520 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SCB9520 +# endif +# define machine_is_scb9520() (machine_arch_type == MACH_TYPE_SCB9520) +#else +# define machine_is_scb9520() (0) +#endif + #ifdef CONFIG_MACH_OMAP_H3 # ifdef machine_arch_type # undef machine_arch_type diff --git a/include/common.h b/include/common.h index 982d6a8..4885c17 100644 --- a/include/common.h +++ b/include/common.h @@ -471,6 +471,7 @@ ulong get_BCLK(void); ulong get_PERCLK1(void); ulong get_PERCLK2(void); ulong get_PERCLK3(void); +void imx_gpio_mode(int); #endif ulong get_bus_freq (ulong); diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h index a4249c4..b86f5b4 100644 --- a/include/configs/scb9328.h +++ b/include/configs/scb9328.h @@ -26,10 +26,41 @@ #define CONFIG_ARM920T 1 /* this is an ARM920T CPU */ #define CONFIG_IMX 1 /* in a Motorola MC9328MXL Chip */ -#define CONFIG_SCB9328 1 /* on a scb9328tronix board */ +#define CONFIG_IMX_DBG 1 /* debug init and stuff */ +#define BOARD_LATE_INIT 1 /* if DBG do some printf */ +#define CONFIG_SCB9328 1 /* on a scb9328 synertronix board */ +#define CONFIG_SCB9328_SNCBRST 1 /* setup sync burts mode flash */ +#define CONFIG_SCB9328_LEDON 1 /* pin 47 of scb9328 low in memsetup.S */ +#undef CONFIG_SCB9328_TOGGLELED /* toggle leds at startup */ +#define CONFIG_DRIVER_NAND 1 /* nand flash support */ +#define CONFIG_DRIVER_DM9000 1 /* dm9000 support */ +#define CONFIG_SERIAL 1 /* serial support */ +#define CONFIG_MISC_INIT_R 1 /* switch "setenv verify" */ +#define CONFIG_BOARD_EARLY_INIT_R 1 #undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */ +#define CFG_FLASH_CFI 1 /* flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ +#define CFG_FLASH_USE_BUFFER_WRITE +#define CFG_ENV_SECT_SIZE 0x00020000 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 259 /* 16MB */ +#define CFG_FLASH_BASE 0x10000000 +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* timeout for Erase operation */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* timeout for Write operation */ +#define CFG_FLASH_PROTECTION 1 +#define CONFIG_AUTO_COMPLETE 1 +#define CFG_HUSH_PARSER 1 +#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING 1 +#define CFG_DEVICE_NULLDEV +#define CFG_LOAD_ADDR 0x08400000 +#define CFG_ENV_IS_NOWHERE 1 +#undef CONFIG_SPLASH_SCREEN +#define CONFIG_SILENT_CONSOLE +#undef CFG_CONSOLE_IS_IN_ENV +#define USE_920T_MMU +#define CFG_CACHELINE_SIZE 32 -#define CONFIG_IMX_SERIAL1 /* * Select serial console configuration */ @@ -40,14 +71,13 @@ * neccessary in include/cmd_confdefs.h file. (Un)comment for getting * functionality or size of u-boot code. */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - & ~CFG_CMD_LOADS \ - & ~CFG_CMD_CONSOLE \ - & ~CFG_CMD_AUTOSCRIPT \ - | CFG_CMD_NET \ - | CFG_CMD_PING \ - | CFG_CMD_DHCP \ - ) +#if !defined (CONFIG_SERIAL) +#define CONFIG_IMX_SERIAL_NONE +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_CACHE | CFG_CMD_BURST & ~CFG_CMD_LOADS & ~CFG_CMD_LOADB & ~CFG_CMD_REISER & ~CFG_CMD_IDE & ~CFG_CMD_SCSI & ~CFG_CMD_USB & ~CFG_CMD_MMC & ~CFG_CMD_PCMCIA & ~CFG_CMD_NAND & ~CFG_CMD_BEDBUG & ~CFG_CMD_BMP & ~CFG_CMD_DISPLAY & ~CFG_CMD_DOC & ~CFG_CMD_DTT & ~CFG_CMD_EEPROM & ~CFG_CMD_EXT2 & ~CFG_CMD_FDC & ~CFG_CMD_FDOS & ~CFG_CMD_MEMORY & ~CFG_CMD_I2C & ~CFG_CMD_ITEST & ~CFG_CMD_PCI & ~CMD_CMD_PORTIO) +#else +#define CONFIG_IMX_SERIAL1 +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_CACHE | CFG_CMD_BURST | CFG_CMD_AUTOSCRIPT) +#endif #include @@ -57,10 +87,11 @@ * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept * parameters at all! Do not get confused by them so. */ -#define CONFIG_BOOTDELAY -1 -#define CONFIG_BOOTARGS "console=ttySMX0,115200n8 root=/dev/mtdblock3 rootfstype=jffs2 mtdparts=scb9328_flash:128k(U-boot)ro,128k(U-boot_env),1m(kernel),4m(root),4m(fs) eval_board=evk9328" +#define CONFIG_BOOTDELAY 1 +#define CONFIG_BOOTARGS "console=ttymxc0,115200n8 root=/dev/mtdblock3 rootfstype=jffs2 mtdparts=physmap-flash.0:128k(U-boot)ro,128k(U-boot_env),2m(kernel),-(root)" +#define CONFIG_EXTRA_ENV_SETTINGS "button=n\0" #define CONFIG_BOOTCOMMAND "bootm 10040000" -#define CONFIG_SHOW_BOOT_PROGRESS +// #define CONFIG_SHOW_BOOT_PROGRESS #define CONFIG_ETHADDR 80:81:82:83:84:85 #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_IPADDR 10.10.10.9 @@ -69,15 +100,15 @@ /* * General options for u-boot. Modify to save memory foot print */ -#define CFG_LONGHELP /* undef saves memory */ -#define CFG_PROMPT "scb9328> " /* prompt string */ +#undef CFG_LONGHELP /* undef saves memory */ +#define CFG_PROMPT "scb9324> " /* prompt string */ #define CFG_CBSIZE 256 /* console I/O buffer */ #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size */ #define CFG_MAXARGS 16 /* max command args */ #define CFG_BARGSIZE CFG_CBSIZE /* boot args buf size */ #define CFG_MEMTEST_START 0x08100000 /* memtest test area */ -#define CFG_MEMTEST_END 0x08F00000 +#define CFG_MEMTEST_END 0x08E00000 #undef CFG_CLKS_IN_HZ /* use HZ for freq. display */ @@ -117,76 +148,20 @@ 0xa10a8300 AutoRefresh Command CAS 3 0xa10a8200 Set AutoRefresh Command CAS 2 */ -#define PRECHARGE_CMD 0x910a8200 -#define AUTOREFRESH_CMD 0xa10a8200 +#define SDCTL0_VAL 0x810a8227 +#define SMODE_NORMAL (0<<28) +#define SMODE_PRECHARGE (1<<28) +#define SMODE_AUTOREFRESH (2<<28) +#define SMODE_MODEREG (3<<28) /* * SDRAM Memory Map */ -/* SH FIXME */ #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ #define SCB9328_SDRAM_1 0x08000000 /* SDRAM bank #1 */ #define SCB9328_SDRAM_1_SIZE 0x01000000 /* 16 MB */ -/* - * Flash Controller settings - */ - -/* - * Hardware drivers - */ - - -/* - * Configuration for FLASH memory for the Synertronixx board - */ - -/* #define SCB9328_FLASH_32M */ - -/* 32MB */ -#ifdef SCB9328_FLASH_32M -#define CFG_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ -#define CFG_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */ -#define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */ -#define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */ -#define SCB9328_FLASH_BANK_SIZE 0x02000000 /* size of one flash bank */ -#define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */ -#define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */ -#define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */ -#else - -/* 16MB */ -#define CFG_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ -#define CFG_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */ -#define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */ -#define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */ -#define SCB9328_FLASH_BANK_SIZE 0x01000000 /* size of one flash bank */ -#define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */ -#define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */ -#define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */ -#endif /* SCB9328_FLASH_32M */ - -/* This should be defined if CFI FLASH device is present. Actually benefit - is not so clear to me. In other words we can provide more informations - to user, but this expects more complex flash handling we do not provide - now.*/ -#undef CFG_FLASH_CFI - -#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* timeout for Erase operation */ -#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* timeout for Write operation */ - -#define CFG_FLASH_BASE SCB9328_FLASH_BASE - -/* - * This is setting for JFFS2 support in u-boot. - * Right now there is no gain for user, but later on booting kernel might be - * possible. Consider using XIP kernel running from flash to save RAM - * footprint. - * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support. - */ -#define CFG_JFFS2_FIRST_BANK 0 -#define CFG_JFFS2_FIRST_SECTOR 5 -#define CFG_JFFS2_NUM_BANKS 1 +#define SEND_MREG_CMD (SCB9328_SDRAM_1 | 0x00223000) /* * Environment setup. Definitions of monitor location and size with @@ -205,6 +180,7 @@ #define CFG_GPR_A_VAL 0x00800000 #define CFG_GIUS_A_VAL 0x0043fffe +#define CFG_GPCR_VAL 0x00000FF8 #define CFG_MONITOR_BASE 0x10000000 #define CFG_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */ @@ -212,145 +188,108 @@ #define CFG_ENV_ADDR 0x10020000 /* absolute address for now */ #define CFG_ENV_SIZE 0x20000 -#define CONFIG_ENV_OVERWRITE 1 /* env is not writable now */ +#define CONFIG_ENV_OVERWRITE 1 /* env is not writable now */ -/* - * CSxU_VAL: - * 63| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x|32 - * |DTACK_SEL|0|BCD | BCS | PSZ|PME|SYNC| DOL | CNC| WSC | 0| WWS | EDC | - * - * CSxL_VAL: - * 31| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x| 0 - * | OEA | OEN | WEA | WEN | CSA |EBC| DSZ | 0|SP|0|WP| 0 0|PA|CSEN| - */ +/* #defines for CS0 where Flash devices are connected to */ -#define CFG_CS0U_VAL 0x000F2000 -#define CFG_CS0L_VAL 0x11110d01 -#define CFG_CS1U_VAL 0x000F0a00 -#define CFG_CS1L_VAL 0x11110601 -#define CFG_CS2U_VAL 0x0 -#define CFG_CS2L_VAL 0x0 - -#define CFG_CS3U_VAL 0x000FFFFF -#define CFG_CS3L_VAL 0x00000303 - -#define CFG_CS4U_VAL 0x000F0a00 -#define CFG_CS4L_VAL 0x11110301 - -/* CNC == 3 too long - #define CFG_CS5U_VAL 0x0000C210 */ - -/* #define CFG_CS5U_VAL 0x00008400 - mal laenger mahcen, ob der bei 150MHz laenger haelt dann und - kaum langsamer ist */ -/* #define CFG_CS5U_VAL 0x00009400 - #define CFG_CS5L_VAL 0x11010D03 */ - -#define CFG_CS5U_VAL 0x00008400 -#define CFG_CS5L_VAL 0x00000D03 - -#define CONFIG_DRIVER_DM9000 1 -#define CONFIG_DRIVER_DM9000 1 -#define CONFIG_DM9000_BASE 0x16000000 -#define DM9000_IO CONFIG_DM9000_BASE -#define DM9000_DATA (CONFIG_DM9000_BASE+4) -/* #define CONFIG_DM9000_USE_8BIT */ -#define CONFIG_DM9000_USE_16BIT -/* #define CONFIG_DM9000_USE_32BIT */ +#define CS0L_DSZ_MASK 0x00000700 -/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1) - f_ref=16,777MHz +/* Failsafe default for all synertronixx devices */ +#define CFG_CS0U_VAL 0x00000900 +#define CFG_CS0L_VAL 0x00000001 - 0x002a141f: 191,9944MHz - 0x040b2007: 144MHz - 0x042a141f: 96MHz - 0x0811140d: 64MHz - 0x040e200e: 150MHz - 0x00321431: 200MHz +#define K3_CS0U_P_VAL 0x00730600 +#define K3_CS0L_P_VAL 0x00000001 - 0x08001800: 64MHz mit 16er Quarz - 0x04001800: 96MHz mit 16er Quarz - 0x04002400: 144MHz mit 16er Quarz +#define P30_CS0U_P_VAL 0x00730900 +#define P30_CS0L_P_VAL 0x00000001 - 31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0 - |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------| */ +#define J3_CS0U_P_VAL 0x00730700 +#define J3_CS0L_P_VAL 0x00000001 -#define CPU200 +#define J3_RCR_P_VAL 0x00004000 +#define J3_RCR_V_VAL 0x00000000 -#ifdef CPU200 -#define CFG_MPCTL0_VAL 0x00321431 -#else -#define CFG_MPCTL0_VAL 0x040e200e -#endif +#ifdef CONFIG_SCB9328_SNCBRST -/* #define BUS64 */ -#define BUS72 +#define FLASH_RCR_CMD 0x60 +#define FLASH_ACK_CMD 0x03 +#define FLASH_K3_ACK_CMD 0x03 +#define FLASH_J3_ACK_CMD 0x04 -#ifdef BUS72 -#define CFG_SPCTL0_VAL 0x04002400 -#endif +#define K3_CS0U_B_VAL 0x10930A00 +#define K3_RCR_B_VAL (2*0x23C3) -#ifdef BUS96 -#define CFG_SPCTL0_VAL 0x04001800 -#endif +#endif /* CONFIG_SCB9328_SNCBRST */ -#ifdef BUS64 -#define CFG_SPCTL0_VAL 0x08001800 -#endif - -/* Das ist der BCLK Divider, der aus der System PLL - BCLK und HCLK erzeugt: - 31 | xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx | 0 - 0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2 - 0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2 - 0x2f001003 : 192MHz/5=38,4MHz - 0x2f000003 : 64MHz/1 - Bit 22: SPLL Restart - Bit 21: MPLL Restart */ - -#ifdef BUS64 -#define CFG_CSCR_VAL 0x2f030003 -#endif - -#ifdef BUS72 -#define CFG_CSCR_VAL 0x2f030403 -#endif - -/* - * Well this has to be defined, but on the other hand it is used differently - * one may expect. For instance loadb command do not cares :-) - * So advice is - do not relay on this... - */ -#define CFG_LOAD_ADDR 0x08400000 +#define CFG_CS1U_VAL 0x00003e78 +#define CFG_CS1L_VAL 0x44448501 -#define MHZ16QUARZINUSE +#define CFG_CS2U_VAL 0x0 +#define CFG_CS2L_VAL 0x0 -#ifdef MHZ16QUARZINUSE -#define CONFIG_SYSPLL_CLK_FREQ 16000000 -#else -#define CONFIG_SYSPLL_CLK_FREQ 16780000 -#endif +#define CFG_CS3U_VAL 0x000ffeff +#define CFG_CS3L_VAL 0x00000303 -#define CONFIG_SYS_CLK_FREQ 16780000 +#ifdef CONFIG_DRIVER_NAND +#define CFG_CS4U_VAL 0x00000200 +#define CFG_CS4L_VAL 0x00000b03 +#define CONFIG_NAND_BASE 0x15000000 +#endif /* CONFIG_DRIVER_NAND */ -/* FMCR Bit 0 becomes 0 to make CS3 CS3 :P */ -#define CFG_FMCR_VAL 0x00000001 +#ifdef CONFIG_DRIVER_DM9000 +#define CFG_CS5U_VAL 0x00000800 +#define CFG_CS5L_VAL 0x00001d03 +#define CONFIG_DM9000_BASE 0x16000000 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE+4) +#define CONFIG_DM9000_USE_16BIT +#endif /* CONFIG_DM9000 */ -/* Bit[0:3] contain PERCLK1DIV for UART 1 - 0x000b00b ->b<- -> 192MHz/12=16MHz - 0x000b00b ->8<- -> 144MHz/09=16MHz - 0x000b00b ->3<- -> 64MHz/4=16MHz */ +/* + * some notes about clock configuration: + * MPCTL0 (cpu clock) 200 MHz (0x00321431) + * + * SPCTL0 (system clock) 144 MHz (0x063a214d) (clk-div 16MHz (0x8)) + * 192 MHz (0x0222158b) (clk-div 16MHz (0xb)) + * scb9328: only 144 MHz; scb9324(v2.x): 192 MHz ok + * u-boot is configured for scb9324 NOT scb9328 + * + * PCDR (clk div) 16 MHz mmc (19.2 MHz maybe ok, too!) + * 16 MHz serial + */ -#ifdef BUS96 -#define CFG_PCDR_VAL 0x000b00b5 -#endif +#define CONFIG_SYSPLL_CLK_FREQ 16780000 +#define CONFIG_MPLL_CLK_FREQ 16780000 +#define CFG_SPCTL0_VAL 0x0222158b +#define CFG_MPCTL0_VAL 0x00321431 +#define CFG_PCDR_VAL 0x000000bb +#define CFG_CSCR_VAL 0x2c000403 +#define CFG_FMCR_VAL 0x00000001 -#ifdef BUS64 -#define CFG_PCDR_VAL 0x000b00b3 -#endif +/* + * The default settings are for SCB9324 only! NAND flash support is enabled and + * the system clock is set to 192 MHz (96 MHz bus clock). + * The following redefinitions are for older SCB9328. They disable NAND flash + * support and set the system clock to 144 MHz (72 MHz bus clock). They + * reconfigure chip select settings for J3 flash and give the beast another + * name, too. Both boards SCB9328 and SCB9324 are running with these settings. + */ -#ifdef BUS72 -#define CFG_PCDR_VAL 0x000b00b8 -#endif +#ifdef BOARD_SCB9328 + +#undef CONFIG_DRIVER_NAND +#undef CFG_PROMPT +#undef J3_CS0U_P_VAL +#undef J3_CS0L_P_VAL +#undef CFG_SPCTL0_VAL +#undef CFG_PCDR_VAL +#define CFG_PROMPT "scb9328> " +#define J3_CS0U_P_VAL 0x00600400 +#define J3_CS0L_P_VAL 0x00060d01 +#define CFG_SPCTL0_VAL 0x063a214d +#define CFG_PCDR_VAL 0x00000088 + +#endif /* BOARD_SCB9328 */ #endif /* __CONFIG_H */ diff --git a/include/configs/scb9520.h b/include/configs/scb9520.h new file mode 100644 index 0000000..b50bc95 --- /dev/null +++ b/include/configs/scb9520.h @@ -0,0 +1,940 @@ +/* + * Copyright (C) 2005 Phytec Messtechnik GmbH + * Juergen Kilb, H. Klaholz + * + * Copyright (C) 2006 Pengutronix + * Sascha Hauer + * Robert Schwebel + * + * Copyright (C) 2007 synertronixx GmbH + * Konstantin Kletschke + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef DEBUG + +/* + * synertronixx scb9520 (PXA270) configuration settings + * Set these to 0/1 to enable or disable the features. + */ + +#define SCB9520_USE_LCD 0 +#define SCB9520_USE_MMC 0 +#define SCB9520_USE_IDE 0 +#define SCB9520_USE_CF 0 +#define SCB9520_USE_FFUART 1 +#define SCB9520_USE_BTUART 0 +#define SCB9520_USE_IRUART 0 +#define SCB9520_USE_AC97 0 +#define SCB9520_USE_SSP 0 +#define SCB9520_USE_SSP3 0 + +#define CONFIG_DRIVER_DM9000 +#define CONFIG_MISC_INIT_R 1 + +/* 260 MHz or 520 MHZ */ +#define SCB9520_SPEED 520 + +/********************************************************************* + * CONFIG PXA270 GPIO settings * + *********************************************************************/ +#if SCB9520_USE_LCD == 1 +/** REG GPSR0 + * GP16 is 1 */ +#define GPSR0_LCD 0x00010000 /* GPIO16 is 1 */ +/** REG GPDR0 + * GP16 == PWM0 is output + ** REG GPDR1 + * GP58 == LDD0 is output + * GP59 == LDD1 is output + * GP60 == LDD2 is output + * GP61 == LDD3 is output + * GP62 == LDD4 is output + * GP63 == LDD5 is output + *** REG GPDR2 + * GP64 == LDD6 is output + * GP65 == LDD7 is output + * GP66 == LDD8 is output + * GP67 == LDD9 is output + * GP68 == LDD10 is output + * GP69 == LDD11 is output + * GP70 == LDD12 is output + * GP71 == LDD13 is output + * GP72 == LDD14 is output + * GP73 == LDD15 is output + * GP74 == LCDFCLK is output + * GP75 == LCDLCLK is output + * GP76 == LCDPCLK is output + * GP77 == LCDBIAS is output */ +#define GPDR0_LCD 0x00010000 /* GPIO 16 Output */ +#define GPDR1_LCD 0xFC000000 /* GPIO 58 - 63 Output */ +#define GPDR2_LCD 0x00003FFF /* GPIO 64 - 77 Output */ +#define GAFR1_U_LCD 0xAAA00000 /* GPIO 58 - 63 AF 02 */ +#define GAFR2_L_LCD 0x0AAAAAAA /* GPIO 64 - 77 AF 02 */ +#else +#define GPDR0_LCD 0x00000000 +#define GPSR0_LCD 0x00000000 +#define GPDR1_LCD 0x00000000 +#define GPDR2_LCD 0x00000000 +#define GAFR1_U_LCD 0x00000000 +#define GAFR2_L_LCD 0x00000000 +#endif + +#if SCB9520_USE_MMC == 1 +/* REG GPDR1 + * GP32 == MMCCLK is output */ +#define GPDR1_MMC 0x00000001 /* GPIO32 is OUTPUT */ +/** REG GAFR1_L + * GP32 == MMCLK is AF10 + ** REG GAFR2_U + * GP92 == MMDAT0 is AF01 + ** REG GAFR3_L + * GP109== MMDAT1 is AF01 + * GP110== MMCS0 is AF01 + * GP111== MMCS1 is AF01 + ** REG GAFR3_U + * GP112== MMCMD is AF01 */ +#define GAFR1_L_MMC 0x00000002 /* GPIO 32 is AF10 */ +#define GAFR2_U_MMC 0x01000000 /* GPIO 92 AF 01 */ +#define GAFR3_L_MMC 0x54000000 /* GPIO 109 - 111 AF 01 */ +#define GAFR3_U_MMC 0x00000001 /* GPIO 112 AF 01 */ +#else +#define GPDR1_MMC 0x00000000 +#define GAFR2_U_MMC 0x00000000 +#define GAFR3_L_MMC 0x00000000 +#define GAFR3_U_MMC 0x00000000 +#endif + +#if ((SCB9520_USE_IDE == 1) || (SCB9520_USE_CF == 1)) +/** REG GPSR1 + * GP48 == nPOE is 1 + * GP49 == nPWE is 1 + * GP50 == nPIOR is 1 + * GP51 == nPIOW is 1 + * GP54 == nPCE2 is 1 + * GP55 == nPREG is 1 + ** REG GPSR2 + * GP85 == nPCE1 is 1 */ +#define GPSR1_IDECF 0x00CF0000 /* GPIO 48-51, 54-55 is 1 */ +#define GPSR2_IDECF 0x00200000 /* GPIO 85 is 1 */ +/* REG GPDR1 + * GP48 == nPOE is output + * GP49 == nPWE is output + * GP50 == nPIOR is output + * GP51 == nPIOW is output + * GP54 == nPCE2 is output + * GP55 == nPREG is output + * REG GPDR2 + * GP79 == PSKTSEL is output + * GP85 == nPCE1 is output */ +#define GPDR1_IDECF 0x00CF0000 /* GPIO 48-51, 54-57 is output */ +#define GPDR2_IDECF 0x00208000 /* GPIO 79,85 is output */ +/** REG GAFR1_U + * GP48 == nPOE is AF10 + * GP49 == nPWE is AF10 + * GP50 == nPIOR is AF10 + * GP51 == nPIOW is AF10 + * GP54 == nPCE2 is AF10 + * GP55 == nPREG is AF10 + * GP56 == nPWAIT is AF01 + * GP57 == nPIOIS16 is AF01 + * REG GAFR2_L + * GP79 == PSKTSEL is AF01 + * REG GAFR2_U + * GP85 == nPCE1 is AF01 */ +#define GAFR1_U_IDECF 0x0005A0AA /* GPIO 48-55 AF 10, 56-57 AF01 */ +#define GAFR2_L_IDECF 0x40000000 /* GPIO 79 AF 01 */ +#define GAFR2_U_IDECF 0x00000400 /* GPIO 85 AF 01 */ +#else +#define GPSR1_IDECF 0x00000000 +#define GPSR2_IDECF 0x00000000 +#define GPDR1_IDECF 0x00000000 +#define GPDR2_IDECF 0x00000000 +#define GAFR1_U_IDECF 0x00000000 +#define GAFR2_L_IDECF 0x00000000 +#define GAFR2_U_IDECF 0x00000000 +#endif + +#if SCB9520_USE_FFUART == 1 +/* REG GPSR1 + * GP41 == FFRTS is 1 */ +#define GPSR1_FFUART 0x00000200 /* GPIO 41 is 1 */ +/* REG GPDR1 + * GP39 == FFTXD is output + * GP40 == FFDTR is output + * GP41 == FFRTS is output */ +#define GPDR1_FFUART 0x00000380 /* GPIO 39-41 is OUTPUT */ +/* REG GAFR1_L + * GP34 == FFRXD is AF01 + * GP35 == FFCTS is AF01 + * GP36 == FFDCD is AF01 + * GP37 == FFDSR is AF01 + * GP38 == FFRI is AF01 + * GP39 == FFTXD is AF10 + * GP40 == FFDTR is AF10 + * GP41 == FFRTS is AF10 */ +#define GAFR1_L_FFUART 0x000A9550 /* GPIO 34-38 is AF01, 39-41 is AF10 */ +#else +#define GPSR1_FFUART 0x00000000 +#define GPDR1_FFUART 0x00000000 +#define GAFR1_L_FFUART 0x00000000 +#endif + +#if SCB9520_USE_BTUART == 1 +/* REG GPSR1 + * GP45 == BTRTS is 1*/ +#define GPSR1_BTUART 0x00002000 /* GPIO 45 is 1 */ +/* REG GPDR1 + * GP43 == BTRXD is output + * GP45 == BTRTS is output */ +#define GPDR1_BTUART 0x00002800 /* GPIO 43,45 is OUTPUT */ +/* REG GAFR1_L + * GP42 == BTRXD is AF01 + * GP43 == BTTXD is AF10 + * GP44 == BTCTS is AF01 + * GP45 == BTRTS is AF10 */ +#define GAFR1_L_BTUART 0x09900000 /* GPIO 42,44 is AF01, 43,45 is AF10 */ +#else +#define GPSR1_BTUART 0x00000000 +#define GPDR1_BTUART 0x00000000 +#define GAFR1_L_BTUART 0x00000000 +#endif + +#if SCB9520_USE_IRUART == 1 +/* REG GPDR1 + * GP47 == STDTXD is output */ +#define GPDR1_IRUART 0x00008000 /* GPIO 47 is OUTPUT */ +/* REG GAFR1_L + * GP46 == STDRXD is AF10 + * GP47 == STDTXD is AF01 */ +#define GAFR1_L_IRUART 0x60000000 /* GPIO 46 is AF10, 47 is AF01 */ +#else +#define GPDR1_IRUART 0x00000000 +#define GAFR1_L_IRUART 0x00000000 +#endif + +#if SCB9520_USE_AC97 == 1 +/* REG GPDR0 + * GP30 == AC97DatO is output + * GP31 == AC97Sync is output + ** REG GPDR3 + * GP113== nAC97_RESET is output */ +#define GPDR0_AC97 0xC0000000 /* GPIO 30,31 is OUTPUT */ +#define GPDR3_AC97 0x00020000 /* GPIO 113 is OUTPUT */ +/* REG GAFR0_L + * GP28 == AC97CLK is AF01 + * GP29 == AC97DatIn is AF01 + * GP30 == AC97DatO is AF10 + * GP31 == AC97SYNC is AF10 + * GP113== AC97_RES is AF10 */ +#define GAFR0_U_AC97 0xA5000000 /* GPIO 28,29 is AF01, 30,31 is AF10 */ +#define GAFR3_U_AC97 0x00000008 /* GPIO 113 is AF10 */ +#else +#define GPDR0_AC97 0x00000000 +#define GPDR3_AC97 0x00000000 +#define GAFR0_U_AC97 0x00000000 +#define GAFR3_U_AC97 0x00000000 +#endif + +#if SCB9520_USE_SSP == 1 +/** REG GPSR0 + * GP24 == SSPSFRM is 1 */ +#define GPSR0_SSP 0x01000000 /* GPIO24 is 1 */ +/* REG GPDR0 + * GP23 == SSPCLK is output + * GP24 == SSPSFRM is output + * GP25 == SSPTXD is output + ** REG GPDR1 + * GP53== SSPSYSCLK is output */ +#define GPDR0_SSP 0x03800000 /* GPIO 23-25 is OUTPUT */ +#define GPDR1_SSP 0x00200000 /* GPIO 53 is OUTPUT */ +/** REG GAFR0_L + * GP23 == SSPSCLK is AF10 + * GP24 == SSPSFRM is AF10 + * GP25 == SSPTXD is AF10 + * GP26 == SSPRXD is AF01 + * GP27 == SSPEXTCLK is AF01 + ** REG GAFR1_U + * GP53 == SSPSYSCLK is AF11 */ +#define GAFR0_U_SSP 0x005A8000 /* GPIO 23-25 is AF10, 26,27 is AF01 */ +#define GAFR1_U_SSP 0x00000C00 /* GPIO 113 is AF10 */ +#else +#define GPSR0_SSP 0x00000000 +#define GPDR0_SSP 0x00000000 +#define GPDR1_SSP 0x00000000 +#define GAFR0_U_SSP 0x00000000 +#define GAFR1_U_SSP 0x00000000 +#endif + +#if SCB9520_USE_SSP3 == 1 +/** REG GPSR2 + * GP83 == SSPSFRM3 is 1 */ +#define GPSR2_SSP3 0x00080000 /* GPIO83 is 1 */ +/* REG GPDR2 + * GP81 == SSPXD3 is output + * GP83 == SSPFRM3 is output + * GP84 == SSPCLK3 is output */ +#define GPDR2_SSP3 0x001A0000 /* GPIO 81,83,84 is OUTPUT */ +/** REG GAFR0_L + * GP81 == SSPTXD3 is AF01 + * GP82 == SSPRXD3 is AF01 + * GP83 == SSPSFRM is AF01 + * GP84 == SSPCLK3 is AF01 */ +#define GAFR2_U_SSP3 0x00000154 /* GPIO 81-84 is AF01 */ +#else +#define GPSR2_SSP3 0x00000000 +#define GPDR2_SSP3 0x00000000 +#define GAFR2_U_SSP3 0x00000000 +#endif + +/* + * GPIO set "1" + * + *** REG GPSR0 + * GP15 == nCS1 is 1 + * GP20 == nSDCS2 is 1 + * GP21 == nSDCS3 is 1 + *** REG GPSR1 + * GP33 == nCS5 is 1 + *** REG GPSR2 + * GP78 == nCS2 is 1 + * GP80 == nCS4 is 1 + */ +#define GPSR0_DFT 0x00308000 +#define GPSR1_DFT 0x00000002 +#define GPSR2_DFT 0x00014000 + +/* setting SDA and ACL to 1 */ +#define GPSR3_DFT 0x00600000 + +#define CFG_GPSR0_VAL GPSR0_DFT | GPSR0_LCD | GPSR0_SSP +#define CFG_GPSR1_VAL GPSR1_DFT | GPSR1_IDECF | GPSR1_FFUART | GPSR1_BTUART +#define CFG_GPSR2_VAL GPSR2_DFT | GPSR2_IDECF | GPSR2_SSP3 +#define CFG_GPSR3_VAL GPSR3_DFT + +/* +#define CFG_GPSR0_VAL 0x01308000 +#define CFG_GPSR1_VAL 0x03CFAA82 +#define CFG_GPSR2_VAL 0x00214000 +#define CFG_GPSR3_VAL 0x00000000 +*/ + +/* + * GPIO clear "0" + */ +#define CFG_GPCR0_VAL 0x00000000 +#define CFG_GPCR1_VAL 0x00000000 +#define CFG_GPCR2_VAL 0x00000000 +#define CFG_GPCR3_VAL 0x00000000 + +/* + * set Direction "1" GPIO == output else input + * + ** REG GPDR0 + * GP03 == PWR_SDA is output + * GP04 == PWR_SCL is output + * GP15 == nCS1 is output + * GP20 == nSDCS2 is output + * GP21 == nSDCS3 is output + ** REG GPDR1 + * GP33 == nCS5 is output + ** REG GPDR2 + * GP78 == nCS2 is output + * GP80 == nCS4 is output + * GP90 == LED0 is output + * GP91 == LED1 is output + ** REG GPDR3 + * GP117== SCL is output + * GP118== SDA is output + */ + +#define GPDR0_DFT 0x00308018 +#define GPDR1_DFT 0x00000002 +#define GPDR2_DFT 0x0C014000 +#define GPDR3_DFT 0x00600000 + +#define CFG_GPDR0_VAL GPDR0_DFT | GPDR0_LCD | GPDR0_AC97 | GPDR0_SSP +#if SCB9520_USE_MMC == 1 +#define CFG_GPDR1_VAL GPDR1_DFT | GPDR1_LCD | GPDR1_MMC | GPDR1_IDECF | GPDR1_FFUART | GPDR1_BTUART | GPDR1_IRUART | GPDR1_SSP +#else +#define CFG_GPDR1_VAL GPDR1_DFT | GPDR1_LCD | GPDR1_IDECF | GPDR1_FFUART | GPDR1_BTUART | GPDR1_IRUART | GPDR1_SSP +#endif +#define CFG_GPDR2_VAL GPDR2_DFT | GPDR2_LCD | GPDR2_SSP3 | GPDR2_IDECF +#define CFG_GPDR3_VAL GPDR3_DFT | GPDR3_AC97 + +/* + * set Alternate Funktions + * + ** REG GAFR0_L + * GP15 == nCS1 is AF10 + ** REG GAFR0_U + * GP18 == RDY is AF01 + * GP20 == nSDCS2 is AF01 + * GP21 == nSDCS3 is AF01 + ** REG GAFR1_L + * GP33 == nCS5 is AF10 + ** REG GAFR2_L + * GP78 == nCS2 is AF10 + ** REG GAFR2_U + * GP80 == nCS4 is AF10 + ** REG GAFR3_U + * GP117== SCL is AF01 + * GP118== SDA is AF01 + */ + +#define GAFR0_L_DFT 0x80000000 +#define GAFR0_U_DFT 0x00000510 +#define GAFR1_L_DFT 0x00000008 +#define GAFR1_U_DFT 0x00000000 +#define GAFR2_L_DFT 0x20000000 +#define GAFR2_U_DFT 0x00000002 +#define GAFR3_L_DFT 0x00000000 +#define GAFR3_U_DFT 0x00001400 + +#define CFG_GAFR0_L_VAL GAFR0_L_DFT +#define CFG_GAFR0_U_VAL GAFR0_U_DFT | GAFR0_U_AC97 | GAFR0_U_SSP +#if SCB9520_USE_MMC == 1 +#define CFG_GAFR1_L_VAL GAFR1_L_DFT | GAFR1_L_FFUART | GAFR1_L_BTUART | GAFR1_L_IRUART | GAFR1_L_MMC +#else +#define CFG_GAFR1_L_VAL GAFR1_L_DFT | GAFR1_L_FFUART | GAFR1_L_BTUART | GAFR1_L_IRUART +#endif +#define CFG_GAFR1_U_VAL GAFR1_U_DFT | GAFR1_U_LCD | GAFR1_U_IDECF | GAFR1_U_SSP +#define CFG_GAFR2_L_VAL GAFR2_L_DFT | GAFR2_L_LCD | GAFR2_L_IDECF +#if SCB9520_USE_MMC == 1 +#define CFG_GAFR2_U_VAL GAFR2_U_DFT | GAFR2_U_IDECF | GAFR2_U_SSP3 | GAFR2_U_MMC +#define CFG_GAFR3_L_VAL GAFR3_L_DFT | GAFR3_L_MMC +#define CFG_GAFR3_U_VAL GAFR3_U_DFT | GAFR3_U_MMC | GAFR3_U_AC97 +#else +#define CFG_GAFR2_U_VAL GAFR2_U_DFT | GAFR2_U_IDECF | GAFR2_U_SSP3 +#define CFG_GAFR3_L_VAL GAFR3_L_DFT +#define CFG_GAFR3_U_VAL GAFR3_U_DFT | GAFR3_U_AC97 +#endif + +/* +#define CFG_GAFR0_L_VAL 0x90000000 +#define CFG_GAFR0_U_VAL 0xA55A859A +#define CFG_GAFR1_L_VAL 0x699A955A +#define CFG_GAFR1_U_VAL 0xAAA5ACAA +#define CFG_GAFR2_L_VAL 0x6AAAAAAA +#define CFG_GAFR2_U_VAL 0x01000556 +#define CFG_GAFR3_L_VAL 0x54000000 +#define CFG_GAFR3_U_VAL 0x00001549 +*/ + +/* + * Power Manager Sleep Status Register (PSSR) + * + * FIXME: RSC: are these registers set correctly??? + * + * [6] = 0 OTG pad is not holding it's state + * [5] = 0 Read Disable Hold: receivers of all gpio pins are disabled + * [4] = 0 gpio pins are held in their sleep mode state + * [3] = 0 The processor has not been placed in standby mode by + * configuring the PWRMODE register since STS was cleared + * by a reset or by software. + * [2] = 0 nVDD_FAULT has been asserted and caused the processor to + * enter deep-sleep mode. + * [1] = 0 nBATT_FAULT has been asserted and caused the processor to + * enter deep-sleep mode. + * [0] = 0 The processor was placed in sleep mode by configuring the + * PWRMODE register. + */ +#define CFG_PSSR_VAL 0x00000020 + + +/********************************************************************* + * CONFIG PXA270 Chipselect settings * + *********************************************************************/ + +/* + * Memory settings + * + * FIXME: RSC: fix documentation + * + * This is the configuration for nCS1/0 -> DIL64 / syncflashpart0 + * configuration for nCS1: + * [31] 0 - Slower Device + * [30:28] 111 - CS deselect to CS time: 7*2+1 = 72ns + * [27:24] 1111 - Address to data valid in bursts: (30+1)*MemClk = 148.8 ns + * [23:20] 1111 - RDF0: - " - for first access: (15+2)*MemClk = 153.6 ns + * [19] 1 - 16 Bit bus width + * [18:16] 001 - SRAM + * configuration for nCS0: + * [15] 0 - Slower Device + * [14:12] 000 - CS deselect to CS time: tOFF = RRRx * 2 + 1 = 0*2+1 = 4.8ns + * [11:08] 0101 - RDN0: Address to data valid in bursts: (5+1)*MemClk = 28.8ns + * [07:04] 1101 - RDF0: - " - for first access: (16+2)*MemClk = 86.5ns + * [03] 1 - 16 Bit bus width + * [02:00] 011 - burst RAM or FLASH + */ +#define CFG_MSC0_VAL 0x7ff905da + +/* + * This is the configuration for nCS3/2 -> DIL64 / DM9000 + * configuration for nCS3: + * + * [31] 0 - Slower Device + * [30:28] 111 - CS deselect to CS time: 7*2+1 = 72ns + * [27:24] 1111 - Address to data valid in bursts: (30+1)*MemClk = 148.8 ns + * [23:20] 1111 - RDF0: - " - for first access: (15+2)*MemClk = 153.6 ns + * [19] 1 - 16 Bit bus width + * [18:16] 001 - SRAM + * configuration for nCS2: + * [15] 0 - Slower Device + * [14:12] 100 - RRR2: CS deselect to CS time: tOFF = RRRx * 2 + 1 = 4*2+1 = 43.2ns + * [11:08] 1101 - RDN2: Address to data valid in bursts: (20+1)*MemClk = 100.8ns + * [07:04] 1101 - RDF2: Address for first access: (20+2)*MemClk = 105.6ns + * [03] 1 - 16 Bit bus width + * [02:00] 001 - SRAM + */ +#define CFG_MSC1_VAL 0x7ff94dd9 + +/* + * This is the configuration for nCS5/4 -> CPLD / CPLD + * + * configuration for nCS5: + * [31] 0 - Slower Device + * [30:28] 111 - CS deselect to CS time: 7*2+1 = 72ns + * [27:24] 1111 - Address to data valid in bursts: (30+1)*MemClk = 148.8 ns + * [23:20] 1111 - RDF0: - " - for first access: (15+2)*MemClk = 153.6 ns + * [19] 1 - 16 Bit bus width + * [18:16] 001 - SRAM + * configuration for nCS4: + * [15] 0 - Slower Device + * [14:12] 011 - RRR4: CS deselect to CS time: 3*2+1 = 33.6ns + * [11:08] 1010 - RDN4: Address to data valid in bursts: (10+1)*MemClk = 52.8ns + * [07:04] 0111 - RDF4: Address for first access: (7+2)*MemClk = 43.2ns + * [03] 1 - 16 Bit bus width + * [02:00] 001 - SRAM + */ +#define CFG_MSC2_VAL 0x7ff93b79 + +/********************************************************************* + * Configuration for FLASH memory * + *********************************************************************/ + +#define CFG_FLASH_CFI 1 /* flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_FLASH_BASE 0x0 +#define CFG_MAX_FLASH_SECT 259 /* 32MB */ +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) +#define CFG_FLASH_PROTECTION 1 + +/********************************************************************* + * CONFIG PXA270 SDRAM settings * + *********************************************************************/ + +/* + * SDRAM Memory Map + */ +#ifndef CONFIG_64MB +#define CONFIG_NR_DRAM_BANKS 2 +#define CFG_SDRAM_1 0xa0000000 +#define CFG_SDRAM_2 0xa4000000 +#else +#define CONFIG_NR_DRAM_BANKS 1 +#define CFG_SDRAM_1 0xa4000000 +#endif + +#define CFG_SDRAM_1_SIZE 0x04000000 +#define CFG_SDRAM_2_SIZE 0x04000000 + +/* MDCNFG: SDRAM Configuration Register FIXME: RSC: check!! + * + * [31] 0 - MDENX : 0: use normal 256Mbyte map + * [30] 0 - DCACX2 + * [29] 0 - reserved + * [28] 0 - SA1111 compatiblity mode + * [27] 1 - SETALWAYS : 1: Always set this bit + * [26] 0 - DADDR2 : alternate addressing for pair 2/3: 0: normal + * [25:24] 01 - DTC2 : 0b01 + * [23] 0 - DNB2 : internal banks in lower partition 2/3 (not used) + * [22:21] 10 - row address bits for partition 2/3 (not used) + * [20:19] 01 - DCAC2 : column address bits for partition 2/3 (not used) + * [18] 0 - SDRAM partition 2/3 width is 32 bit + * [17] 0 - SDRAM partition 3 disabled + * [16] 0 - SDRAM partition 2 disabled + * [15] 0 - Stack1 + * [14] 0 - DCACX0 + * [13] 1 - Stack0 + * [12] 0 - SA1110 compatiblity mode + * [11] 1 - SETALWAYS : always 1 + * [10] 0 - no alternate addressing for pair 0/1 + * [09:08] 01 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk + * [7] 1 - 4 internal banks in lower partition pair + * [06:05] 10 - 13 row address bits for partition 0/1 + * [04:03] 01 - DCAC0 : 0b001: 9 column address bits for partition 0/1 + * [02] 0 - SDRAM partition 0/1 width is 32 bit + * [01] 1 - enable SDRAM partition 1 + * [00] 1 - enable SDRAM partition 0 + * 0 x 0000 1001 0100 1000 | 0010 1001 0100 1011 + */ +#ifndef CONFIG_64MB +#define CFG_MDCNFG_VAL 0x094829cb +#else +#define CFG_MDCNFG_VAL 0x094829ca +#endif + +/* MDREFR: SDRAM Refresh Control Register + * + * [31] 0 - ALTREFA + * [30] 0 - ALTREFB + * [29] 1 - K0DB4 : 1: divide CLK_MEM by four to generate SDCLK<0> and SDCLK<3> + - and OVERRIDE K0DB2 + * [28] 0 - reserved + * [27] 0 - reserved + * [26] 0 - reserved + * [25] 0 - K2FREE: 0: disable free running to switch it off by K2RUN + * [24] 0 - K1FREE: not free running (K1RUN determines actual state) + * [23] 0 - K0FREE: not free running (SDCLK<1> and SDCLK<3> depend on K0RUN) + * [22] 1 - SLFRSH: self refresh enabled + * [21] 0 - reserved + * [20] 0 - APD: no automatic powerdown FIXME: MAKE THIS WORK + * [19] 0 - K2DB2: SDCLK2 is MemClk + * [18] 0 - K2RUN: 0: look at K2FREE + * [17] 1 - K1DB2: SDCLK1 is MemClk/2 + * [16] 1 - K1RUN: enable SDCLK1 FIXME: 0: look at APD + * [15] 1 - E1PIN: SDRAM clock enable + * [14] 1 - K0DB2: SDCLK0 is MemClk/2 (overriden by K0DB4) + * [13] 1 - K0RUN: enable SDCLK0 FIXME: 0: look at APD + * [12] 0 - RESERVED + * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24 + * 0 x 0010 0000 0100 0011 | 1110 0000 0001 1000 + */ +//#define CFG_MDREFR_VAL 0x2043E018 +/* FIXME: + * for now this seems to work okay: */ +#define CFG_MDREFR_VAL 0x2213e018 + +/* MDMRS: Mode Register Set Configuration Register + * + * [31] 0 - reserved + * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used) + * [22:20] 000 - MDCL2: SDRAM2/3 Cas Latency. (not used) + * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used) + * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used) + * [15] 0 - reserved + * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value. + * [06:04] 010 - MDCL0: SDRAM0/1 Cas Latency. + * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential. + * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4. + */ +#define CFG_MDMRS_VAL 0x00220022 + +/* lower driverstrength from default val 5 */ +#define CFG_BSCNTR_VAL 0x33333333 + +#define CFG_FLYCNFG_VAL 0x00010001 + +/* [31] 0 - SXCLEXT2 + * [30] 0 - reserved + * [29:28] 00 - SXTP2 : 0b11 burst 16 + * [27:21] 0000000 - reserved + * [20:18] 000 - SXCL2 : 0b1000 9 clocks (frequency configuration code 8) + * [17] 0 - SXEN3 + * [16] 0 - SXEN2 + * [15] 0 - SXCLEXT0 + * [14] 0 - reserved + * [13:12] 10 - SXTP0 + * [11:5] 0000000 - reserved + * [4:2] 100 - SXCL0 : 0b0100 5 clocks (frequency configuration code = 4) + * [1] 0 - SXEN1 + * [0] 1 - SXEN0 + */ +#define CFG_SXCNFG_VAL 0xb000b001 + +#define CFG_CKEN 0x00500660 /* Memory, Int.Memory, OS Timer, FFUART, STUART, USB-HOST */ + +#if SCB9520_SPEED == 520 +#define CFG_CCCR 0x02000290 +#elif SCB9520_SPEED == 260 +#define CFG_CCCR 0x02000288 +#else +#error You have specified an illegal speed. +#endif + +#define CFG_CPUSPEED CFG_CCCR + +/********************************************************************* + * CONFIG PXA270 CF interface * + *********************************************************************/ +#define CFG_MECR_VAL 0x00000003 +#define CFG_MCMEM0_VAL 0x00010504 +#define CFG_MCMEM1_VAL 0x00010504 +#define CFG_MCATT0_VAL 0x00010504 +#define CFG_MCATT1_VAL 0x00010504 +#define CFG_MCIO0_VAL 0x00004715 +#define CFG_MCIO1_VAL 0x00004715 + +/********************************************************************* + * CONFIG PXA270 IDE interface * + *********************************************************************/ +#if ((SCB9520_USE_IDE == 1) || (SCB9520_USE_CF == 1)) +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_ATAPI 1 +#define CONFIG_SUPORT_VFAT 1 +#define CONFIG_PXA_PCMCIA 1 +#define CONFIG_PXA_IDE 1 +#undef CONFIG_IDE_LED /* no led supported */ +#define CONFIG_PCMCIA_SLOT_A 1 /* just to keep build system happy */ +#define CFG_PCMCIA_MEM_ADDR 0x38000000 +#define CFG_PCMCIA_MEM_SIZE 0x04000000 + +#if ((SCB9520_USE_IDE == 1) && (SCB9520_USE_CF == 1)) +#define CFG_IDE_MAXBUS 2 /* max. 2 IDE bus */ +#define CFG_IDE_MAXDEVICE 4 /* max. 2 drive per IDE bus */ +#define CFG_ATA_BASE_ADDR 0x20000000 +#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CFG_ATA_IDE1_OFFSET 0x10000000 +#endif +#if ((SCB9520_USE_IDE == 1) && (SCB9520_USE_CF == 0)) +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 2 /* max. 2 drive per IDE bus */ +#define CFG_ATA_BASE_ADDR 0x20000000 +#define CFG_ATA_IDE0_OFFSET 0x0000 +#endif +#if ((SCB9520_USE_IDE == 0) && (SCB9520_USE_CF == 1)) +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ +#define CFG_ATA_BASE_ADDR 0x30000000 +#define CFG_ATA_IDE0_OFFSET 0x0000 +#endif + +#define CFG_ATA_DATA_OFFSET 0x0 +#define CFG_ATA_REG_OFFSET 0x0 +#define CFG_ATA_ALT_OFFSET 0x800 +#endif +/********************************************************************* + * CONFIG PXA270 MMC interface * + *********************************************************************/ +#if SCB9520_USE_MMC == 1 +#define CONFIG_MMC 1 +#define CFG_MMC_BASE 0xF0000000 +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_SUPORT_VFAT 1 +#endif +/********************************************************************* + * CONFIG Ethernet DM9000 * + *********************************************************************/ + +#ifdef CONFIG_DRIVER_DM9000 +#define CONFIG_DM9000_BASE 0x08000000 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE+4) +#define CONFIG_DM9000_USE_16BIT +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_ETHADDR 00:C7:F0:00:00:01 +#define CONFIG_NETMASK 255.255.0.0 +#define CONFIG_IPADDR 10.10.10.9 +#define CONFIG_SERVERIP 10.10.10.10 +#endif + +/********************************************************************* + * CONFIG PXA270 LCD * + *********************************************************************/ +#if SCB9520_USE_LCD == 1 +#define CONFIG_LCD +#define CONFIG_SHARP_LQ084V1DG21 +#endif +/********************************************************************* + * CONFIG PXA270 I2C * + *********************************************************************/ +#if 1 +#define DEBUG_I2C 1 +#define CONFIG_HARD_I2C 1 +#define CFG_I2C_SPEED 400000 +#define CFG_I2C_SLAVE 0xfe +#define CFG_I2C_EEPROM_ADDR 0x54 /* A0=0, A1=0 (hardwired) */ + /* without R/W-Bit ! */ +#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 15 /* between stop and start */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 /* length of byte address */ +#define CFG_EEPROM_SIZE 4096 /* size in bytes */ +#define CFG_I2C_INIT_BOARD /* board hasn't it's own init */ +#define BOARD_LATE_INIT 1 +#endif + + +/* + ##################################################################### + # # + # U-BOOT settings # + # # + ##################################################################### + */ + +/* + * If we are developing, we might want to start armboot from ram + * so we MUST NOT initialize critical regs like mem-timing ... + */ +#define RTC +/* + * Select u-boot PXA270 configuration + */ +#define CONFIG_PXA27X 1 /* this is an PXA270 CPU */ +#define CONFIG_SCB9520 1 /* config for synertronixx board */ +#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */ +#define CONFIG_AUTO_COMPLETE 1 +#define CFG_HUSH_PARSER 1 +#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING 1 + + +/* + * Select serial console configuration + */ +#define CONFIG_FFUART 1 /* FFUART is default */ +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Select support for RTC PCF8564 (fully comp. to PCF8563 from Philips) + */ +#if 0 +#define CONFIG_RTC_PCF8563 1 +#define CFG_I2C_RTC_ADDR 0x51 +#endif + +/* + * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if + * neccessary in include/cmd_confdefs.h file. (Un)comment for getting + * functionality or size of u-boot code. + */ +#if ((SCB9520_USE_IDE == 1) || (SCB9520_USE_CF == 1) || (SCB9520_USE_MMC == 1)) +#define CONFIG_STORAGE_COMMANDS CFG_CMD_FAT | CFG_CMD_EXT2 +#endif + +#if ((SCB9520_USE_IDE == 1) || (SCB9520_USE_CF == 1)) +#define CONFIG_IDECF_COMMANDS CFG_CMD_IDE | CFG_CMD_PCMCIA +#endif + +#if (SCB9520_USE_MMC == 1) +#define CONFIG_MMC_COMMANDS CFG_CMD_MMC +#endif + +#ifdef CONFIG_DRIVER_DM9000 +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + & ~CFG_CMD_GPIOPXA \ + & ~CFG_CMD_CHGGPIO \ + | CFG_CMD_I2C \ + | CFG_CMD_AUTOSCRIPT \ + & ~CFG_CMD_DATE \ + ) +#else +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL \ + & ~CFG_CMD_NET \ + & ~CFG_CMD_MISC \ + & ~CFG_CMD_NAND \ + ) +#endif + +#include + +#undef CONFIG_SPLASH_SCREEN +#define CONFIG_SILENT_CONSOLE +#undef CFG_CONSOLE_IS_IN_ENV + +/* + * low level support for gdb debugger + * + */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Boot options. Setting delay to -1 stops autostart count down. + */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_SERVERIP 10.10.10.10 +#define CONFIG_BOOTARGS "console=ttySA0,115200n8 root=/dev/mtdblock3 rootfstype=jffs2 mtdparts=physmap-flash.0:128k(U-boot)ro,128k(U-boot_env),2m(kernel),-(root)" +#define CONFIG_BOOTCOMMAND "bootm 40000" + +/* + * General options for u-boot. Modify to save memory foot print + */ +#define CFG_LONGHELP /* undef saves memory */ +#define CFG_PROMPT "scb9520> " /* prompt string */ +#define CFG_CBSIZE 1024 /* console I/O buffer */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size */ +#define CFG_MAXARGS 16 /* max command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* boot args buf size */ + +#define CFG_MEMTEST_START (CFG_SDRAM_1 + 0x400000) /* memtest area sta */ +#define CFG_MEMTEST_END (CFG_SDRAM_1 + 0x800000) /* memtest area end */ + +#undef CFG_CLKS_IN_HZ /* use HZ for freq. display */ +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ + +/* + * Definitions related to passing arguments to kernel. + */ +#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */ +#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */ +#define CONFIG_INITRD_TAG 1 /* send initrd params */ +#undef CONFIG_VFD /* do not send framebuffer setup */ + + +/* + * Malloc pool need to host env + 128 Kb reserve for other allocations. + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + (128<<10)) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CONFIG_STACKSIZE (120<<10) /* stack size */ + +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */ +#endif + +/* + * Environment setup. Definitions of monitor location and size with + * definition of environment setup ends up in 2 possibilities. + * 1. Embeded environment - in u-boot code is space for environment + * 2. Environment is read from predefined sector of flash + * Right now we support 2. possiblity, but expecting no env placed + * on mentioned address right now. This also needs to provide whole + * sector for it - for us 256Kb is really waste of memory. U-boot uses + * default env. and until kernel parameters could be sent to kernel + * env. has no sense to us. + */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN 0x20000 /* 128kb ( 1 flash sector ) */ +#define CFG_ENV_IS_IN_FLASH 1 /* we store ENV in EEPROM */ +#define CONFIG_ENV_OVERWRITE /* env is not writable now */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR 0x20000 +#define CFG_ENV_SIZE 0x20000 +#define CFG_ENV_SECT_SIZE 0x20000 + +/* + * Well this has to be defined, but on the other hand it is used differently + * one may expect. For instance loadb command do not cares :-) + * So advice is - do not relay on this... + */ +#define CFG_LOAD_ADDR 0xa4000000 + +#endif /* __CONFIG_H */ diff --git a/include/flash.h b/include/flash.h index 8b7e824..159b6b9 100644 --- a/include/flash.h +++ b/include/flash.h @@ -33,6 +33,9 @@ typedef struct { ulong size; /* total bank size in bytes */ ushort sector_count; /* number of erase units */ ulong flash_id; /* combined device & manufacturer code */ + ulong rcr_val; /* don't understand the "combined" in flash_id */ + ulong cs0u_val; /* don't understand the "combined" in flash_id */ + ulong cs0l_val; /* don't understand the "combined" in flash_id */ ulong start[CFG_MAX_FLASH_SECT]; /* physical sector start addresses */ uchar protect[CFG_MAX_FLASH_SECT]; /* sector protection status */ #ifdef CFG_FLASH_CFI diff --git a/include/lcd.h b/include/lcd.h index b688583..1d755b3 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -77,7 +77,7 @@ typedef struct vidinfo { extern vidinfo_t panel_info; -#elif defined CONFIG_PXA250 +#elif (defined CONFIG_PXA250 || defined CONFIG_PXA27X) /* * PXA LCD DMA descriptor */